Searched refs:FSL_CORENET_DEVDISR5_DDR3 (Results 1 - 2 of 2) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dcpu.c106 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h1347 #define FSL_CORENET_DEVDISR5_DDR3 0x20000000 macro

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