Searched refs:DDRC_PCFGQOS1_0 (Results 1 - 8 of 8) sorted by relevance
/u-boot/board/mntre/imx8mq_reform2/ |
H A D | lpddr4_timing.c | 107 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
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/u-boot/board/purism/librem5/ |
H A D | lpddr4_timing_b0.c | 125 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
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H A D | lpddr4_timing.c | 90 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
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/u-boot/board/freescale/imx8mq_evk/ |
H A D | lpddr4_timing.c | 90 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
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H A D | lpddr4_timing_b0.c | 125 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
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/u-boot/arch/arm/include/asm/arch-imx8m/ |
H A D | ddr.h | 522 #define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) macro
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/u-boot/board/ronetix/imx8mq-cm/ |
H A D | lpddr4_timing.c | 90 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
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/u-boot/board/beacon/imx8mm/ |
H A D | lpddr4_timing.c | 73 { DDRC_PCFGQOS1_0(0), 0x00620096 },
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