Searched refs:DDRC_PCFGQOS1_0 (Results 1 - 8 of 8) sorted by relevance

/u-boot/board/mntre/imx8mq_reform2/
H A Dlpddr4_timing.c107 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
/u-boot/board/purism/librem5/
H A Dlpddr4_timing_b0.c125 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
H A Dlpddr4_timing.c90 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing.c90 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
H A Dlpddr4_timing_b0.c125 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h522 #define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) macro
/u-boot/board/ronetix/imx8mq-cm/
H A Dlpddr4_timing.c90 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
/u-boot/board/beacon/imx8mm/
H A Dlpddr4_timing.c73 { DDRC_PCFGQOS1_0(0), 0x00620096 },

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