Searched refs:DDRC_DRAMTMG17 (Results 1 - 8 of 8) sorted by relevance
| /u-boot/board/mntre/imx8mq_reform2/ |
| H A D | lpddr4_timing.c | 38 { DDRC_DRAMTMG17(0), 0x00a00050 },
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| /u-boot/board/purism/librem5/ |
| H A D | lpddr4_timing_b0.c | 43 { DDRC_DRAMTMG17(0), 0x00A00050 },
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| H A D | lpddr4_timing.c | 41 { DDRC_DRAMTMG17(0), 0x00A00050 },
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| /u-boot/board/freescale/imx8mq_evk/ |
| H A D | lpddr4_timing.c | 41 { DDRC_DRAMTMG17(0), 0x00A00050 },
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| H A D | lpddr4_timing_b0.c | 43 { DDRC_DRAMTMG17(0), 0x00A00050 },
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| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| H A D | ddr.h | 430 #define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) macro
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| /u-boot/board/ronetix/imx8mq-cm/ |
| H A D | lpddr4_timing.c | 41 { DDRC_DRAMTMG17(0), 0x00A00050 },
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| /u-boot/board/beacon/imx8mm/ |
| H A D | lpddr4_timing.c | 34 { DDRC_DRAMTMG17(0), 0x00A00050 },
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