Searched refs:CVMX_LMCX_DDR_PLL_CTL (Results 1 - 3 of 3) sorted by relevance
| /u-boot/drivers/ram/octeon/ |
| H A D | octeon_ddr.c | 578 ddr_pll_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(0));
612 lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(0), ddr_pll_ctl.u64);
666 lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(1), ddr_pll_ctl.u64);
844 lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i));
854 lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(i), ddr_pll_ctl.u64);
874 lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i));
888 lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i));
890 lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(i), ddr_pll_ctl.u64);
896 lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i));
937 CVMX_LMCX_DDR_PLL_CTL(
[all...] |
| H A D | octeon3_lmc.c | 9781 lmcx_ddr_pll_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(lmc));
10742 lmc_ddr_pll_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(0));
10787 ddr_pll_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(0));
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| /u-boot/arch/mips/mach-octeon/include/mach/ |
| H A D | cvmx-lmcx-defs.h | 55 #define CVMX_LMCX_DDR_PLL_CTL(offs) \ macro
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