Searched refs:CR_I (Results 1 - 5 of 5) sorted by relevance

/u-boot/arch/arm/mach-uniphier/arm32/
H A Dpsci_smp.S15 orr r1, r1, #CR_I @ Enable ICache
/u-boot/arch/arm/lib/
H A Dcache-cp15.c214 /* cache_bit must be either CR_I or CR_C */
233 /* cache_bit must be either CR_I or CR_C */
279 cache_enable(CR_I);
284 cache_disable(CR_I);
289 return (get_cr() & CR_I) != 0;
/u-boot/arch/arm/include/asm/
H A Dsystem.h16 #define CR_I (1 << 12) /* Icache enable */ macro
330 #define CR_I (1 << 12) /* Icache enable */ macro
/u-boot/arch/arm/cpu/armv8/
H A Dcache_v8.c787 set_sctlr(get_sctlr() | CR_I);
792 set_sctlr(get_sctlr() & ~CR_I);
797 return (get_sctlr() & CR_I) != 0;
H A Dcache.S253 /* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */
254 movn x1, #(CR_M | CR_C | CR_I)

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