#
95167db3 |
|
10-Mar-2024 |
Lukasz Wiecaszek <lukasz.wiecaszek@googlemail.com> |
arm: Check FEAT_CCIDX when parsing ccsidr_el1 register Current Cache Size ID Register (ccsidr_el1) has two "flavors" depending on whether FEAT_CCIDX is implemented or not. When FEAT_CCIDX is implemented Associativity parameter is coded on bits [23:3] and NumSets parameter on bits [55:32]. When FEAT_CCIDX is not implemented then Associativity parameter is coded on bits [12:3] and NumSets parameter on bits [27:13]. Current U-Boot code does not check whether FEAT_CCIDX is implemented and always parses ccsidr_el1 as if FEAT_CCIDX was not implemented. This is of course wrong on systems where FEAT_CCIDX is implemented. This patch fixes that problems and tests whether FEAT_CCIDX is implemented or not and accordingly parses the ccsidr_el1 register. Signed-off-by: Lukasz Wiecaszek <lukasz.wiecaszek@gmail.com> |
#
46dc5428 |
|
08-Feb-2023 |
Marc Zyngier <maz@kernel.org> |
arm: cpu: Add optional CMOs by VA Exposing set/way cache maintenance to a virtual machine is unsafe, not least because the instructions are not permission-checked but also because they are not broadcast between CPUs. Consequently, KVM traps and emulates such maintenance in the host kernel using by-VA operations and looping over the stage-2 page-tables. However, when running under protected KVM, these instructions are not able to be emulated and will instead result in an exception being delivered to the guest. Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select this option and perform by-VA cache maintenance instead of using the set/way instructions. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Will Deacon <willdeacon@google.com> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> [ Paul: pick from the Android tree. Fixup Pierre's commit. And fix some checkpatch warnings. Rebased to upstream. ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/db5507f47f4f57f766d52f753ff2cc761afc213b Link: https://android.googlesource.com/platform/external/u-boot/+/2baf54e743380a1e4a6bc2dbdde020a2e783ff67 |
#
37479e65 |
|
27-Aug-2021 |
Pierre-Clément Tosi <ptosi@google.com> |
armv8/cache.S: Triple with single instruction Replace the current 2-instruction 2-step tripling code by a corresponding single instruction leveraging ARMv8-A's "flexible second operand as a register with optional shift". This has the added benefit (albeit arguably negligible) of reducing the final code size. Fix the comment as the tripled cache level is placed in x12, not x0. Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> |
#
f050bfac |
|
27-Aug-2021 |
Pierre-Clément Tosi <ptosi@google.com> |
armv8/cache.S: Read sysreg fields through ubfx Improve the file's readability and conciseness by using the appropriate Aarch64 instruction: ubfx (unsigned bitfield extract). This makes the code easier to follow as it directly manipulates the offsets and widths of the fields read from system registers, as they are expressed in the Standard (ARM ARM). This has the added benefit (albeit arguably negligible) of reducing the final code size. Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> |
#
f7b845bf |
|
29-Jun-2021 |
Tom Rini <trini@konsulko.com> |
arm: armv8: Fix warning about redeclaring global functions as weak As seen with clang-12: warning: __asm_invalidate_l3_dcache changed binding to STB_WEAK As we indeed use ENTRY and then declare the function weak manually. Use the WEAK declarative from <linux/linkage.h> instead. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e6a05862 |
|
04-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
armv8: move low-level assembly functions into function-sections TPL builds today don't need to call into firmware or set up the MMU (if this changes, it should be controlled through a config option whether to include this or not), but include the needed support code for this anyway. By moving these unused low-level functions into seperate function-sections, the linker can garbage-collect the unused sections. Note that (if DM support is enabled), there will be a call to the cache-flushing code from alloc_priv(...) in drivers/core/device.c. This then add 52 bytes of binary size (an increase from 20589 to 20641 bytes) compared to completely removing this code. Even for a feature-rich TPL (including DM support as for the RK3368), this equates to a size difference of significantly more than 10% in TPL binary size. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
ba9eb6c7 |
|
17-May-2016 |
Masahiro Yamada <masahiroy@kernel.org> |
arm64: rename __asm_flush_dcache_level to __asm_dcache_level Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
1a021230 |
|
17-May-2016 |
Masahiro Yamada <masahiroy@kernel.org> |
arm64: fix comment "flush & invalidate" We should say "clean & invalidate", or simply "flush". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
25828588 |
|
17-May-2016 |
Masahiro Yamada <masahiroy@kernel.org> |
arm64: optimize __asm_{flush, invalidate}_dcache_all __asm_dcache_all can directly return to the caller of __asm_{flush,invalidate}_dcache_all. We do not have to waste x16 register here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
208bd513 |
|
06-Aug-2015 |
Peng Fan <Peng.Fan@freescale.com> |
arm: armv8 correct value passed to __asm_dcache_all >From source code comments: "x0: 0 flush & invalidate, 1 invalidate only" Current value 0xffff can make invalidate work, since we only judge whether input value is 0 or not, see following code: " tbz w1, #0, 1f dc isw, x9 b 2f 1: dc cisw, x9 /* clean & invalidate by set/way */ 2: subs x6, x6, #1 /* decrement the way */ " Later we may add "2 clean only" support. So following the comments, correct value from 0xffff to 1. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> |
#
7682a998 |
|
17-Mar-2015 |
Rob Herring <robh@kernel.org> |
remove unnecessary version.h includes Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
f1075aed |
|
14-Jan-2015 |
Michal Simek <michal.simek@amd.com> |
ARM: armv8: Fix typo in commentary Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
42ddfad6 |
|
30-Mar-2014 |
Leo Yan <leoy@marvell.com> |
ARMv8: fix bug for flush data cache by set/way When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
46dc5428 |
|
08-Feb-2023 |
Marc Zyngier <maz@kernel.org> |
arm: cpu: Add optional CMOs by VA Exposing set/way cache maintenance to a virtual machine is unsafe, not least because the instructions are not permission-checked but also because they are not broadcast between CPUs. Consequently, KVM traps and emulates such maintenance in the host kernel using by-VA operations and looping over the stage-2 page-tables. However, when running under protected KVM, these instructions are not able to be emulated and will instead result in an exception being delivered to the guest. Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select this option and perform by-VA cache maintenance instead of using the set/way instructions. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Will Deacon <willdeacon@google.com> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> [ Paul: pick from the Android tree. Fixup Pierre's commit. And fix some checkpatch warnings. Rebased to upstream. ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/db5507f47f4f57f766d52f753ff2cc761afc213b Link: https://android.googlesource.com/platform/external/u-boot/+/2baf54e743380a1e4a6bc2dbdde020a2e783ff67 |
#
37479e65 |
|
27-Aug-2021 |
Pierre-Clément Tosi <ptosi@google.com> |
armv8/cache.S: Triple with single instruction Replace the current 2-instruction 2-step tripling code by a corresponding single instruction leveraging ARMv8-A's "flexible second operand as a register with optional shift". This has the added benefit (albeit arguably negligible) of reducing the final code size. Fix the comment as the tripled cache level is placed in x12, not x0. Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> |
#
f050bfac |
|
27-Aug-2021 |
Pierre-Clément Tosi <ptosi@google.com> |
armv8/cache.S: Read sysreg fields through ubfx Improve the file's readability and conciseness by using the appropriate Aarch64 instruction: ubfx (unsigned bitfield extract). This makes the code easier to follow as it directly manipulates the offsets and widths of the fields read from system registers, as they are expressed in the Standard (ARM ARM). This has the added benefit (albeit arguably negligible) of reducing the final code size. Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> |
#
f7b845bf |
|
29-Jun-2021 |
Tom Rini <trini@konsulko.com> |
arm: armv8: Fix warning about redeclaring global functions as weak As seen with clang-12: warning: __asm_invalidate_l3_dcache changed binding to STB_WEAK As we indeed use ENTRY and then declare the function weak manually. Use the WEAK declarative from <linux/linkage.h> instead. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e6a05862 |
|
04-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
armv8: move low-level assembly functions into function-sections TPL builds today don't need to call into firmware or set up the MMU (if this changes, it should be controlled through a config option whether to include this or not), but include the needed support code for this anyway. By moving these unused low-level functions into seperate function-sections, the linker can garbage-collect the unused sections. Note that (if DM support is enabled), there will be a call to the cache-flushing code from alloc_priv(...) in drivers/core/device.c. This then add 52 bytes of binary size (an increase from 20589 to 20641 bytes) compared to completely removing this code. Even for a feature-rich TPL (including DM support as for the RK3368), this equates to a size difference of significantly more than 10% in TPL binary size. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
ba9eb6c7 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: rename __asm_flush_dcache_level to __asm_dcache_level Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
1a021230 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: fix comment "flush & invalidate" We should say "clean & invalidate", or simply "flush". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
25828588 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: optimize __asm_{flush, invalidate}_dcache_all __asm_dcache_all can directly return to the caller of __asm_{flush,invalidate}_dcache_all. We do not have to waste x16 register here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
208bd513 |
|
06-Aug-2015 |
Peng Fan <Peng.Fan@freescale.com> |
arm: armv8 correct value passed to __asm_dcache_all >From source code comments: "x0: 0 flush & invalidate, 1 invalidate only" Current value 0xffff can make invalidate work, since we only judge whether input value is 0 or not, see following code: " tbz w1, #0, 1f dc isw, x9 b 2f 1: dc cisw, x9 /* clean & invalidate by set/way */ 2: subs x6, x6, #1 /* decrement the way */ " Later we may add "2 clean only" support. So following the comments, correct value from 0xffff to 1. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> |
#
7682a998 |
|
17-Mar-2015 |
Rob Herring <robh@kernel.org> |
remove unnecessary version.h includes Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
f1075aed |
|
14-Jan-2015 |
Michal Simek <michal.simek@amd.com> |
ARM: armv8: Fix typo in commentary Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
42ddfad6 |
|
30-Mar-2014 |
Leo Yan <leoy@marvell.com> |
ARMv8: fix bug for flush data cache by set/way When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
37479e65 |
|
27-Aug-2021 |
Pierre-Clément Tosi <ptosi@google.com> |
armv8/cache.S: Triple with single instruction Replace the current 2-instruction 2-step tripling code by a corresponding single instruction leveraging ARMv8-A's "flexible second operand as a register with optional shift". This has the added benefit (albeit arguably negligible) of reducing the final code size. Fix the comment as the tripled cache level is placed in x12, not x0. Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> |
#
f050bfac |
|
27-Aug-2021 |
Pierre-Clément Tosi <ptosi@google.com> |
armv8/cache.S: Read sysreg fields through ubfx Improve the file's readability and conciseness by using the appropriate Aarch64 instruction: ubfx (unsigned bitfield extract). This makes the code easier to follow as it directly manipulates the offsets and widths of the fields read from system registers, as they are expressed in the Standard (ARM ARM). This has the added benefit (albeit arguably negligible) of reducing the final code size. Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> |
#
f7b845bf |
|
29-Jun-2021 |
Tom Rini <trini@konsulko.com> |
arm: armv8: Fix warning about redeclaring global functions as weak As seen with clang-12: warning: __asm_invalidate_l3_dcache changed binding to STB_WEAK As we indeed use ENTRY and then declare the function weak manually. Use the WEAK declarative from <linux/linkage.h> instead. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e6a05862 |
|
04-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
armv8: move low-level assembly functions into function-sections TPL builds today don't need to call into firmware or set up the MMU (if this changes, it should be controlled through a config option whether to include this or not), but include the needed support code for this anyway. By moving these unused low-level functions into seperate function-sections, the linker can garbage-collect the unused sections. Note that (if DM support is enabled), there will be a call to the cache-flushing code from alloc_priv(...) in drivers/core/device.c. This then add 52 bytes of binary size (an increase from 20589 to 20641 bytes) compared to completely removing this code. Even for a feature-rich TPL (including DM support as for the RK3368), this equates to a size difference of significantly more than 10% in TPL binary size. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
ba9eb6c7 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: rename __asm_flush_dcache_level to __asm_dcache_level Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
1a021230 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: fix comment "flush & invalidate" We should say "clean & invalidate", or simply "flush". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
25828588 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: optimize __asm_{flush, invalidate}_dcache_all __asm_dcache_all can directly return to the caller of __asm_{flush,invalidate}_dcache_all. We do not have to waste x16 register here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
208bd513 |
|
06-Aug-2015 |
Peng Fan <Peng.Fan@freescale.com> |
arm: armv8 correct value passed to __asm_dcache_all >From source code comments: "x0: 0 flush & invalidate, 1 invalidate only" Current value 0xffff can make invalidate work, since we only judge whether input value is 0 or not, see following code: " tbz w1, #0, 1f dc isw, x9 b 2f 1: dc cisw, x9 /* clean & invalidate by set/way */ 2: subs x6, x6, #1 /* decrement the way */ " Later we may add "2 clean only" support. So following the comments, correct value from 0xffff to 1. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> |
#
7682a998 |
|
17-Mar-2015 |
Rob Herring <robh@kernel.org> |
remove unnecessary version.h includes Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
f1075aed |
|
14-Jan-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM: armv8: Fix typo in commentary Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
42ddfad6 |
|
30-Mar-2014 |
Leo Yan <leoy@marvell.com> |
ARMv8: fix bug for flush data cache by set/way When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
f7b845bf |
|
29-Jun-2021 |
Tom Rini <trini@konsulko.com> |
arm: armv8: Fix warning about redeclaring global functions as weak As seen with clang-12: warning: __asm_invalidate_l3_dcache changed binding to STB_WEAK As we indeed use ENTRY and then declare the function weak manually. Use the WEAK declarative from <linux/linkage.h> instead. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e6a05862 |
|
04-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
armv8: move low-level assembly functions into function-sections TPL builds today don't need to call into firmware or set up the MMU (if this changes, it should be controlled through a config option whether to include this or not), but include the needed support code for this anyway. By moving these unused low-level functions into seperate function-sections, the linker can garbage-collect the unused sections. Note that (if DM support is enabled), there will be a call to the cache-flushing code from alloc_priv(...) in drivers/core/device.c. This then add 52 bytes of binary size (an increase from 20589 to 20641 bytes) compared to completely removing this code. Even for a feature-rich TPL (including DM support as for the RK3368), this equates to a size difference of significantly more than 10% in TPL binary size. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
ba9eb6c7 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: rename __asm_flush_dcache_level to __asm_dcache_level Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
1a021230 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: fix comment "flush & invalidate" We should say "clean & invalidate", or simply "flush". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
25828588 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: optimize __asm_{flush, invalidate}_dcache_all __asm_dcache_all can directly return to the caller of __asm_{flush,invalidate}_dcache_all. We do not have to waste x16 register here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
208bd513 |
|
06-Aug-2015 |
Peng Fan <Peng.Fan@freescale.com> |
arm: armv8 correct value passed to __asm_dcache_all >From source code comments: "x0: 0 flush & invalidate, 1 invalidate only" Current value 0xffff can make invalidate work, since we only judge whether input value is 0 or not, see following code: " tbz w1, #0, 1f dc isw, x9 b 2f 1: dc cisw, x9 /* clean & invalidate by set/way */ 2: subs x6, x6, #1 /* decrement the way */ " Later we may add "2 clean only" support. So following the comments, correct value from 0xffff to 1. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> |
#
7682a998 |
|
17-Mar-2015 |
Rob Herring <robh@kernel.org> |
remove unnecessary version.h includes Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
f1075aed |
|
14-Jan-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM: armv8: Fix typo in commentary Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
42ddfad6 |
|
30-Mar-2014 |
Leo Yan <leoy@marvell.com> |
ARMv8: fix bug for flush data cache by set/way When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e6a05862 |
|
04-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
armv8: move low-level assembly functions into function-sections TPL builds today don't need to call into firmware or set up the MMU (if this changes, it should be controlled through a config option whether to include this or not), but include the needed support code for this anyway. By moving these unused low-level functions into seperate function-sections, the linker can garbage-collect the unused sections. Note that (if DM support is enabled), there will be a call to the cache-flushing code from alloc_priv(...) in drivers/core/device.c. This then add 52 bytes of binary size (an increase from 20589 to 20641 bytes) compared to completely removing this code. Even for a feature-rich TPL (including DM support as for the RK3368), this equates to a size difference of significantly more than 10% in TPL binary size. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
ba9eb6c7 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: rename __asm_flush_dcache_level to __asm_dcache_level Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
1a021230 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: fix comment "flush & invalidate" We should say "clean & invalidate", or simply "flush". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
25828588 |
|
17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: optimize __asm_{flush, invalidate}_dcache_all __asm_dcache_all can directly return to the caller of __asm_{flush,invalidate}_dcache_all. We do not have to waste x16 register here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
208bd513 |
|
06-Aug-2015 |
Peng Fan <Peng.Fan@freescale.com> |
arm: armv8 correct value passed to __asm_dcache_all >From source code comments: "x0: 0 flush & invalidate, 1 invalidate only" Current value 0xffff can make invalidate work, since we only judge whether input value is 0 or not, see following code: " tbz w1, #0, 1f dc isw, x9 b 2f 1: dc cisw, x9 /* clean & invalidate by set/way */ 2: subs x6, x6, #1 /* decrement the way */ " Later we may add "2 clean only" support. So following the comments, correct value from 0xffff to 1. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> |
#
7682a998 |
|
17-Mar-2015 |
Rob Herring <robh@kernel.org> |
remove unnecessary version.h includes Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
f1075aed |
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14-Jan-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM: armv8: Fix typo in commentary Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
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42ddfad6 |
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30-Mar-2014 |
Leo Yan <leoy@marvell.com> |
ARMv8: fix bug for flush data cache by set/way When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com> |
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1e6ad55c |
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26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
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0ae76531 |
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13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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e6a05862 |
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04-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
armv8: move low-level assembly functions into function-sections TPL builds today don't need to call into firmware or set up the MMU (if this changes, it should be controlled through a config option whether to include this or not), but include the needed support code for this anyway. By moving these unused low-level functions into seperate function-sections, the linker can garbage-collect the unused sections. Note that (if DM support is enabled), there will be a call to the cache-flushing code from alloc_priv(...) in drivers/core/device.c. This then add 52 bytes of binary size (an increase from 20589 to 20641 bytes) compared to completely removing this code. Even for a feature-rich TPL (including DM support as for the RK3368), this equates to a size difference of significantly more than 10% in TPL binary size. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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6775a820 |
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05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
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1ab557a0 |
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19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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ba9eb6c7 |
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17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: rename __asm_flush_dcache_level to __asm_dcache_level Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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1a021230 |
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17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: fix comment "flush & invalidate" We should say "clean & invalidate", or simply "flush". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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25828588 |
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17-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: optimize __asm_{flush, invalidate}_dcache_all __asm_dcache_all can directly return to the caller of __asm_{flush,invalidate}_dcache_all. We do not have to waste x16 register here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com>
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5e2ec773 |
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03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de>
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208bd513 |
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06-Aug-2015 |
Peng Fan <Peng.Fan@freescale.com> |
arm: armv8 correct value passed to __asm_dcache_all >From source code comments: "x0: 0 flush & invalidate, 1 invalidate only" Current value 0xffff can make invalidate work, since we only judge whether input value is 0 or not, see following code: " tbz w1, #0, 1f dc isw, x9 b 2f 1: dc cisw, x9 /* clean & invalidate by set/way */ 2: subs x6, x6, #1 /* decrement the way */ " Later we may add "2 clean only" support. So following the comments, correct value from 0xffff to 1. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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7682a998 |
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17-Mar-2015 |
Rob Herring <robh@kernel.org> |
remove unnecessary version.h includes Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
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dcd468b8 |
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06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com>
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f1075aed |
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14-Jan-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM: armv8: Fix typo in commentary Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
42ddfad6 |
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30-Mar-2014 |
Leo Yan <leoy@marvell.com> |
ARMv8: fix bug for flush data cache by set/way When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com>
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#
1e6ad55c |
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26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
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#
0ae76531 |
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13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn>
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