/u-boot/dts/upstream/include/dt-bindings/clock/ |
H A D | mt8135-clk.h | 41 #define CLK_TOP_SYSPLL_D5 30 macro
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H A D | mt7629-clk.h | 42 #define CLK_TOP_SYSPLL_D5 32 macro
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/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 45 #define CLK_TOP_SYSPLL_D5 32 macro
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H A D | mt8512-clk.h | 21 #define CLK_TOP_SYSPLL_D5 10 macro
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H A D | mt8183-clk.h | 44 #define CLK_TOP_SYSPLL_D5 8 macro
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/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 45 #define CLK_TOP_SYSPLL_D5 32 macro
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H A D | mt8512-clk.h | 21 #define CLK_TOP_SYSPLL_D5 10 macro
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H A D | mt8183-clk.h | 44 #define CLK_TOP_SYSPLL_D5 8 macro
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/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 45 #define CLK_TOP_SYSPLL_D5 32 macro
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H A D | mt8512-clk.h | 21 #define CLK_TOP_SYSPLL_D5 10 macro
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/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 45 #define CLK_TOP_SYSPLL_D5 32 macro
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H A D | mt8512-clk.h | 21 #define CLK_TOP_SYSPLL_D5 10 macro
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H A D | mt8183-clk.h | 44 #define CLK_TOP_SYSPLL_D5 8 macro
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/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 45 #define CLK_TOP_SYSPLL_D5 32 macro
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H A D | mt8512-clk.h | 21 #define CLK_TOP_SYSPLL_D5 10 macro
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H A D | mt8183-clk.h | 44 #define CLK_TOP_SYSPLL_D5 8 macro
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/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 45 #define CLK_TOP_SYSPLL_D5 32 macro
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H A D | mt8512-clk.h | 21 #define CLK_TOP_SYSPLL_D5 10 macro
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H A D | mt8183-clk.h | 44 #define CLK_TOP_SYSPLL_D5 8 macro
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/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 45 #define CLK_TOP_SYSPLL_D5 32 macro
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H A D | mt8512-clk.h | 21 #define CLK_TOP_SYSPLL_D5 10 macro
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H A D | mt8183-clk.h | 44 #define CLK_TOP_SYSPLL_D5 8 macro
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/u-boot/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 45 #define CLK_TOP_SYSPLL_D5 32 macro
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H A D | mt8512-clk.h | 21 #define CLK_TOP_SYSPLL_D5 10 macro
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/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7623.c | 105 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), 114 FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2), 115 FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4), 190 CLK_TOP_SYSPLL_D5, 229 CLK_TOP_SYSPLL_D5, 429 CLK_TOP_SYSPLL_D5 441 CLK_TOP_SYSPLL_D5, 459 CLK_TOP_SYSPLL_D5,
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