| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8183.c | 83 FACTOR(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1,
97 FACTOR(CLK_TOP_SYSPLL_D3_D2, CLK_TOP_SYSPLL_D3, 1,
99 FACTOR(CLK_TOP_SYSPLL_D3_D4, CLK_TOP_SYSPLL_D3, 1,
101 FACTOR(CLK_TOP_SYSPLL_D3_D8, CLK_TOP_SYSPLL_D3, 1,
204 CLK_TOP_SYSPLL_D3,
214 CLK_TOP_SYSPLL_D3,
225 CLK_TOP_SYSPLL_D3,
239 CLK_TOP_SYSPLL_D3,
251 CLK_TOP_SYSPLL_D3,
263 CLK_TOP_SYSPLL_D3,
[all...] |
| H A D | clk-mt8365.c | 85 PLL_FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", CLK_APMIXED_MAINPLL, 1, 3),
147 CLK_TOP_SYSPLL_D3,
168 CLK_TOP_SYSPLL_D3,
175 CLK_TOP_SYSPLL_D3,
364 CLK_TOP_SYSPLL_D3,
402 CLK_TOP_SYSPLL_D3,
417 CLK_TOP_SYSPLL_D3,
|
| H A D | clk-mt7623.c | 104 FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
111 FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2),
112 FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4),
113 FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8),
244 CLK_TOP_SYSPLL_D3,
409 CLK_TOP_SYSPLL_D3,
|
| H A D | clk-mt8512.c | 81 FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
170 CLK_TOP_SYSPLL_D3,
315 CLK_TOP_SYSPLL_D3,
336 CLK_TOP_SYSPLL_D3,
343 CLK_TOP_SYSPLL_D3,
407 CLK_TOP_SYSPLL_D3,
|
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 39 #define CLK_TOP_SYSPLL_D3 28 macro
|
| H A D | mediatek,mt6795-clk.h | 56 #define CLK_TOP_SYSPLL_D3 45 macro
|
| H A D | mt6765-clk.h | 41 #define CLK_TOP_SYSPLL_D3 6 macro
|
| H A D | mt6797-clk.h | 51 #define CLK_TOP_SYSPLL_D3 41 macro
|
| H A D | mt8173-clk.h | 58 #define CLK_TOP_SYSPLL_D3 48 macro
|
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 17 #define CLK_TOP_SYSPLL_D3 6 macro
|
| H A D | mt8183-clk.h | 43 #define CLK_TOP_SYSPLL_D3 7 macro
|
| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 17 #define CLK_TOP_SYSPLL_D3 6 macro
|
| H A D | mt8183-clk.h | 43 #define CLK_TOP_SYSPLL_D3 7 macro
|
| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 17 #define CLK_TOP_SYSPLL_D3 6 macro
|
| H A D | mt8183-clk.h | 43 #define CLK_TOP_SYSPLL_D3 7 macro
|
| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 17 #define CLK_TOP_SYSPLL_D3 6 macro
|
| H A D | mt8183-clk.h | 43 #define CLK_TOP_SYSPLL_D3 7 macro
|
| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 17 #define CLK_TOP_SYSPLL_D3 6 macro
|
| H A D | mt8183-clk.h | 43 #define CLK_TOP_SYSPLL_D3 7 macro
|
| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 17 #define CLK_TOP_SYSPLL_D3 6 macro
|
| H A D | mt8183-clk.h | 43 #define CLK_TOP_SYSPLL_D3 7 macro
|
| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 17 #define CLK_TOP_SYSPLL_D3 6 macro
|
| H A D | mt8183-clk.h | 43 #define CLK_TOP_SYSPLL_D3 7 macro
|
| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 17 #define CLK_TOP_SYSPLL_D3 6 macro
|
| H A D | mt8183-clk.h | 43 #define CLK_TOP_SYSPLL_D3 7 macro
|