Searched refs:CLK_TOP_FA2SYS_SEL (Results 1 - 9 of 9) sorted by relevance

/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt8518-clk.h115 #define CLK_TOP_FA2SYS_SEL 93 macro
/u-boot/include/dt-bindings/clock/
H A Dmt8518-clk.h115 #define CLK_TOP_FA2SYS_SEL 93 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt8518-clk.h115 #define CLK_TOP_FA2SYS_SEL 93 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt8518-clk.h115 #define CLK_TOP_FA2SYS_SEL 93 macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt8518-clk.h115 #define CLK_TOP_FA2SYS_SEL 93 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt8518-clk.h115 #define CLK_TOP_FA2SYS_SEL 93 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt8518-clk.h115 #define CLK_TOP_FA2SYS_SEL 93 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt8518-clk.h115 #define CLK_TOP_FA2SYS_SEL 93 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt8518.c1215 MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3),
1466 GATE_TOP5_I(CLK_TOP_FA2SYS, CLK_TOP_FA2SYS_SEL, 8),

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