Searched refs:CLK_APMIXED_UNIVPLL (Results 1 - 25 of 48) sorted by relevance

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/u-boot/drivers/clk/mediatek/
H A Dclk-mt8365.c46 PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22,
96 PLL_FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", CLK_APMIXED_UNIVPLL, 1, 2),
97 PLL_FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", CLK_APMIXED_UNIVPLL, 1, 4),
98 PLL_FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", CLK_APMIXED_UNIVPLL, 1, 8),
99 PLL_FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", CLK_APMIXED_UNIVPLL, 1, 3),
100 PLL_FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", CLK_APMIXED_UNIVPLL, 1, 6),
101 PLL_FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", CLK_APMIXED_UNIVPLL, 1, 12),
102 PLL_FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", CLK_APMIXED_UNIVPLL, 1, 24),
103 PLL_FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", CLK_APMIXED_UNIVPLL, 1, 96),
104 PLL_FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", CLK_APMIXED_UNIVPLL,
[all...]
H A Dclk-mt8516.c41 PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
84 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
85 FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
86 FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
87 FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
88 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
89 FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
90 FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
91 FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
92 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL,
[all...]
H A Dclk-mt7623.c49 PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
119 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1),
120 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
121 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
122 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
123 FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7),
124 FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26),
125 FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52),
126 FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108),
127 FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL,
[all...]
H A Dclk-mt8518.c41 PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
86 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
87 FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
88 FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
89 FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
90 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
91 FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
92 FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
93 FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
94 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL,
[all...]
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt8135-clk.h111 #define CLK_APMIXED_UNIVPLL 4 macro
H A Dmt8516-clk.h15 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmediatek,mt6795-clk.h143 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt6797-clk.h109 #define CLK_APMIXED_UNIVPLL 2 macro
/u-boot/arch/arm/mach-mediatek/mt8516/
H A Dinit.c48 [CLK_APMIXED_UNIVPLL] = 1248000000,
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h16 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt8518-clk.h13 #define CLK_APMIXED_UNIVPLL 2 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h16 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt8518-clk.h13 #define CLK_APMIXED_UNIVPLL 2 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h16 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt8518-clk.h13 #define CLK_APMIXED_UNIVPLL 2 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h16 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt8518-clk.h13 #define CLK_APMIXED_UNIVPLL 2 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h16 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt8518-clk.h13 #define CLK_APMIXED_UNIVPLL 2 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h16 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt8518-clk.h13 #define CLK_APMIXED_UNIVPLL 2 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h16 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt8518-clk.h13 #define CLK_APMIXED_UNIVPLL 2 macro
/u-boot/include/dt-bindings/clock/
H A Dmt8516-clk.h16 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt8518-clk.h13 #define CLK_APMIXED_UNIVPLL 2 macro

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