| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 18 #define CLK_APMIXED_MFGPLL 7 macro
|
| H A D | mediatek,mt8365-clk.h | 236 #define CLK_APMIXED_MFGPLL 3 macro
|
| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 18 #define CLK_APMIXED_MFGPLL 7 macro
|
| H A D | mediatek,mt8365-clk.h | 236 #define CLK_APMIXED_MFGPLL 3 macro
|
| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 18 #define CLK_APMIXED_MFGPLL 7 macro
|
| H A D | mediatek,mt8365-clk.h | 236 #define CLK_APMIXED_MFGPLL 3 macro
|
| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 18 #define CLK_APMIXED_MFGPLL 7 macro
|
| H A D | mediatek,mt8365-clk.h | 236 #define CLK_APMIXED_MFGPLL 3 macro
|
| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 18 #define CLK_APMIXED_MFGPLL 7 macro
|
| H A D | mediatek,mt8365-clk.h | 236 #define CLK_APMIXED_MFGPLL 3 macro
|
| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 18 #define CLK_APMIXED_MFGPLL 7 macro
|
| H A D | mediatek,mt8365-clk.h | 236 #define CLK_APMIXED_MFGPLL 3 macro
|
| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 18 #define CLK_APMIXED_MFGPLL 7 macro
|
| H A D | mediatek,mt8365-clk.h | 236 #define CLK_APMIXED_MFGPLL 3 macro
|
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 18 #define CLK_APMIXED_MFGPLL 7 macro
|
| H A D | mediatek,mt8365-clk.h | 236 #define CLK_APMIXED_MFGPLL 3 macro
|
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt6765-clk.h | 14 #define CLK_APMIXED_MFGPLL 4 macro
|
| H A D | mt6797-clk.h | 110 #define CLK_APMIXED_MFGPLL 3 macro
|
| H A D | mediatek,mt8365-clk.h | 234 #define CLK_APMIXED_MFGPLL 3 macro
|
| H A D | mt6779-clk.h | 175 #define CLK_APMIXED_MFGPLL 10 macro
|
| H A D | mt8183-clk.h | 18 #define CLK_APMIXED_MFGPLL 7 macro
|
| H A D | mt8186-clk.h | 274 #define CLK_APMIXED_MFGPLL 10 macro
|
| H A D | mt8192-clk.h | 307 #define CLK_APMIXED_MFGPLL 6 macro
|
| H A D | mediatek,mt8188-clk.h | 314 #define CLK_APMIXED_MFGPLL 14 macro
|
| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 48 PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24,
109 PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1),
|