Searched refs:CFG_SYS_MPC85xx_L2_OFFSET (Results 1 - 2 of 2) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dstart.S83 #define CFG_SYS_MPC85xx_L2_OFFSET 0x20000 define
130 .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
133 .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
136 .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h2538 #define CFG_SYS_MPC85xx_L2_OFFSET 0x20000 macro
2616 (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_L2_OFFSET)

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