Searched refs:ACPI_BASE_ADDRESS (Results 1 - 10 of 10) sorted by relevance

/u-boot/arch/x86/cpu/broadwell/
H A Dpower_state.c35 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
68 ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
69 ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
70 ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
71 ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
72 ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
73 ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
74 ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
75 ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
76 ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS
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H A Dpch.c48 dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1);
93 clrsetio_32(ACPI_BASE_ADDRESS + PM1_CNT, SLP_TYP, SCI_EN);
138 outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0));
139 outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32));
140 outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64));
141 outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
578 * setio_16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT);
H A Dnorthbridge.c31 pei_data->pmbase = ACPI_BASE_ADDRESS;
/u-boot/arch/x86/include/asm/arch-braswell/
H A Diomap.h41 #define ACPI_BASE_ADDRESS 0x400 macro
/u-boot/arch/x86/include/asm/arch-broadwell/
H A Diomap.h36 #define ACPI_BASE_ADDRESS 0x1000 macro
/u-boot/arch/x86/include/asm/arch-apollolake/
H A Diomap.h20 #define ACPI_BASE_ADDRESS IOMAP_ACPI_BASE macro
/u-boot/arch/x86/cpu/baytrail/
H A Dacpi.c27 u16 pmbase = ACPI_BASE_ADDRESS;
172 * FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS
189 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
190 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
209 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
210 outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
/u-boot/arch/x86/include/asm/arch-baytrail/
H A Diomap.h82 #define ACPI_BASE_ADDRESS 0x0400 macro
/u-boot/arch/x86/cpu/intel_common/
H A Dacpi.c359 acpigen_write_processor(ctx, core_id, is_first ? ACPI_BASE_ADDRESS : 0,
/u-boot/arch/x86/include/asm/
H A Dmsr-index.h82 #define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14)

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