| /seL4-test-master/tools/riscv-pk/machine/ |
| H A D | fp_ldst.c | 8 return write_csr(mbadaddr, addr), (handler)(regs, mcause, mepc)
16 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
31 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
41 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
56 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
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| H A D | emulation.c | 19 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
24 return misaligned_load_trap(regs, mcause, mepc);
29 return misaligned_load_trap(regs, mcause, mepc);
34 return misaligned_store_trap(regs, mcause, mepc);
39 return misaligned_store_trap(regs, mcause, mepc);
46 return misaligned_load_trap(regs, mcause, mepc);
51 return misaligned_load_trap(regs, mcause, mepc);
56 return misaligned_store_trap(regs, mcause, mepc);
61 return misaligned_store_trap(regs, mcause, mepc);
68 return truly_illegal_insn(regs, mcause, mep
71 illegal_insn_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc) argument
[all...] |
| H A D | fp_emulation.c | 49 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
56 return f(regs, mcause, mepc, mstatus, insn);
62 void emulate_any_fadd(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc, uintptr_t mstatus, insn_t insn, int32_t neg_b) argument
73 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
79 return emulate_any_fadd(regs, mcause, mepc, mstatus, insn, 0);
84 return emulate_any_fadd(regs, mcause, mepc, mstatus, insn, INT32_MIN);
98 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
113 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
120 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
127 return truly_illegal_insn(regs, mcause, mep
[all...] |
| H A D | misaligned_ldst.c | 16 void misaligned_load_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc) argument
68 mcause = CAUSE_LOAD_ACCESS;
69 write_csr(mcause, mcause);
70 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
87 void misaligned_store_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc) argument
135 mcause = CAUSE_STORE_ACCESS;
136 write_csr(mcause, mcause);
137 return truly_illegal_insn(regs, mcause, mep
[all...] |
| H A D | mtrap.c | 22 die("machine mode: unhandlable trap %d @ %p", read_csr(mcause), mepc);
132 void mcall_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc) argument
203 write_csr(scause, read_csr(mcause));
217 void pmp_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc) argument
234 uintptr_t mcause = read_csr(mcause); local
236 switch (mcause)
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| H A D | emulation.h | 12 #define DECLARE_EMULATION_FUNC(name) void name(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc, uintptr_t mstatus, insn_t insn)
14 void misaligned_load_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc);
15 void misaligned_store_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc);
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| H A D | muldiv_emulation.c | 37 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
60 return truly_illegal_insn(regs, mcause, mepc, mstatus, insn);
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| H A D | fp_emulation.h | 46 else if (GET_RM(insn) > 4) return truly_illegal_insn(regs, mcause, mepc, mstatus, insn); \
67 else if (GET_RM(insn) > 4) return truly_illegal_insn(regs, mcause, mepc, mstatus, insn); \
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| H A D | mentry.S | 46 csrr a1, mcause
49 # This is an interrupt. Discard the mcause MSB and decode the rest.
115 sll t1, a1, 2 # t1 <- mcause << 2
117 add t1, t0, t1 # t1 <- %hi(trap_table)[mcause]
119 LWU t1, %pcrel_lo(1b)(t1) # t1 <- trap_table[mcause]
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| H A D | encoding.h | 1308 DECLARE_CSR(mcause, CSR_MCAUSE)
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