Searched refs:CLK_ENET (Results 1 - 4 of 4) sorted by relevance

/seL4-test-master/projects/util_libs/libplatsupport/plat_include/imx7/platsupport/plat/
H A Dclock.h19 CLK_ENET, /* 630-1300MHz, set to 1000MHz */ enumerator in enum:clk_id
/seL4-test-master/projects/util_libs/libplatsupport/plat_include/imx6/platsupport/plat/
H A Dclock.h22 CLK_ENET, enumerator in enum:clk_id
37 CLK_PLL6 = CLK_ENET,
/seL4-test-master/projects/util_libs/libplatsupport/src/plat/imx6/
H A Dclock.c680 [CLK_ENET] = &enet_clk,
698 [CLK_ENET] = 48 * MHZ,
/seL4-test-master/projects/util_libs/libethdrivers/src/plat/imx6/
H A Denet.c544 enet_clk_ptr = clk_get_clock(clk_sys, CLK_ENET);

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