1/*
2 * Copyright 2017, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
8 * See "LICENSE_BSD2.txt" for details.
9 *
10 * @TAG(DATA61_BSD)
11 */
12
13#pragma once
14
15enum clk_id {
16    CLK_MASTER,
17    CLK_PLL2,
18    CLK_MMDC_CH0,
19    CLK_AHB,
20    CLK_IPG,
21    CLK_ARM,
22    CLK_ENET,
23    CLK_USB1,
24    CLK_USB2,
25    CLK_CLKO1,
26    CLK_CLKO2,
27    /* ----- */
28    NCLOCKS,
29    /* Custom clock */
30    CLK_CUSTOM,
31    /* Aliases */
32    CLK_PLL1 = CLK_ARM,
33//  CLK_PLL2 = CLK_SYS
34    CLK_PLL3 = CLK_USB1,
35//  CLK_PLL4 = CLK_AUDIO,
36//  CLK_PLL5 = CLK_VIDEO,
37    CLK_PLL6 = CLK_ENET,
38    CLK_PLL7 = CLK_USB2,
39//  CLK_PLL8 = CLK_MLB,
40    CLK_PERCLK = CLK_IPG,
41};
42
43#define CLK_GATE(reg, index)  (((reg) << 4) + (index))
44enum clock_gate {
45    /* -- CCGR0 -- */
46    /* -- CCGR1 -- */
47    /* -- CCGR2 -- */
48    ocotp_ctrl   = CLK_GATE(2, 6),
49    i2c3_serial  = CLK_GATE(2, 5),
50    i2c2_serial  = CLK_GATE(2, 4),
51    i2c1_serial  = CLK_GATE(2, 3),
52    /* -- CCGR3 -- */
53    ipu1_ipu     = CLK_GATE(3, 0),
54    ipu1_ipu_di0 = CLK_GATE(3, 1),
55    ipu1_ipu_di1 = CLK_GATE(3, 2),
56    ipu2_ipu     = CLK_GATE(3, 3),
57    ipu2_ipu_di0 = CLK_GATE(3, 4),
58    ipu2_ipu_di1 = CLK_GATE(3, 5),
59    /* -- CCGR4 -- */
60    /* -- CCGR5 -- */
61
62    /* -- CCGR6 -- */
63    usboh3       = CLK_GATE(6, 0),
64    usdhc1       = CLK_GATE(6, 1),
65    usdhc2       = CLK_GATE(6, 2),
66    usdhc3       = CLK_GATE(6, 3),
67    usdhc4       = CLK_GATE(6, 4),
68    eim_slow     = CLK_GATE(6, 5),
69    vdoaxiclk    = CLK_GATE(6, 6),
70    vpu          = CLK_GATE(6, 7),
71    NCLKGATES
72};
73
74