Searched refs:TOP (Results 1 - 10 of 10) sorted by relevance

/seL4-refos-master/libs/libplatsupport/src/plat/exynos5/
H A Dexynos_5422_clock.h23 #define CLKID_SCLKCPLL CLKID(TOP, 8, 0)
24 #define CLKID_SCLKDPLL CLKID(TOP, 10, 0)
25 #define CLKID_SCLKEPLL CLKID(TOP, 12, 0)
26 #define CLKID_SCLKRPLL CLKID(TOP, 16, 0)
27 #define CLKID_SCLKIPLL CLKID(TOP, 20, 0)
28 #define CLKID_SCLDVPLL CLKID(TOP, 24, 0)
29 #define CLKID_SCLKVPLL CLKID(TOP, 28, 0)
30 #define CLKID_SCLKMPLL CLKID(TOP, 32, 0)
H A Dexynos_common_clock.h21 #define CLKID_SCLKCPLL CLKID(TOP, 6, 2)
22 #define CLKID_SCLKEPLL CLKID(TOP, 6, 3)
23 #define CLKID_SCLKVPLL CLKID(TOP, 6, 4)
24 #define CLKID_SCLKGPLL CLKID(TOP, 6, 7)
H A Dclock.c47 #define CLKID_UART0 CLKID(TOP, 20, 0)
48 #define CLKID_UART1 CLKID(TOP, 20, 1)
49 #define CLKID_UART2 CLKID(TOP, 20, 2)
50 #define CLKID_UART3 CLKID(TOP, 20, 3)
51 #define CLKID_PWM CLKID(TOP, 20, 5)
52 #define CLKID_SPI0 CLKID(TOP, 21, 4)
53 #define CLKID_SPI1 CLKID(TOP, 21, 5)
54 #define CLKID_SPI2 CLKID(TOP, 21, 6)
55 #define CLKID_SPI0_ISP CLKID(TOP, 28, 0)
56 #define CLKID_SPI1_ISP CLKID(TOP, 2
[all...]
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos5/
H A Dexynos_5422_clock.h23 #define CLKID_SCLKCPLL CLKID(TOP, 8, 0)
24 #define CLKID_SCLKDPLL CLKID(TOP, 10, 0)
25 #define CLKID_SCLKEPLL CLKID(TOP, 12, 0)
26 #define CLKID_SCLKRPLL CLKID(TOP, 16, 0)
27 #define CLKID_SCLKIPLL CLKID(TOP, 20, 0)
28 #define CLKID_SCLDVPLL CLKID(TOP, 24, 0)
29 #define CLKID_SCLKVPLL CLKID(TOP, 28, 0)
30 #define CLKID_SCLKMPLL CLKID(TOP, 32, 0)
H A Dexynos_common_clock.h21 #define CLKID_SCLKCPLL CLKID(TOP, 6, 2)
22 #define CLKID_SCLKEPLL CLKID(TOP, 6, 3)
23 #define CLKID_SCLKVPLL CLKID(TOP, 6, 4)
24 #define CLKID_SCLKGPLL CLKID(TOP, 6, 7)
H A Dclock.c47 #define CLKID_UART0 CLKID(TOP, 20, 0)
48 #define CLKID_UART1 CLKID(TOP, 20, 1)
49 #define CLKID_UART2 CLKID(TOP, 20, 2)
50 #define CLKID_UART3 CLKID(TOP, 20, 3)
51 #define CLKID_PWM CLKID(TOP, 20, 5)
52 #define CLKID_SPI0 CLKID(TOP, 21, 4)
53 #define CLKID_SPI1 CLKID(TOP, 21, 5)
54 #define CLKID_SPI2 CLKID(TOP, 21, 6)
55 #define CLKID_SPI0_ISP CLKID(TOP, 28, 0)
56 #define CLKID_SPI1_ISP CLKID(TOP, 2
[all...]
/seL4-refos-master/libs/libplatsupport/src/plat/exynos4/
H A Dclock.c54 #define CLKID_SCLKEPLL CLKID(TOP , 4, 1)
55 #define CLKID_SCLKVPLL CLKID(TOP , 4, 2)
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos4/
H A Dclock.c54 #define CLKID_SCLKEPLL CLKID(TOP , 4, 1)
55 #define CLKID_SCLKVPLL CLKID(TOP , 4, 2)
/seL4-refos-master/projects/refos/impl/apps/nethack/src/nethack-3.4.3/src/
H A Dsp_lev.c54 #define TOP 1 macro
484 case TOP:
2138 case TOP: ystart = 3; break;
/seL4-refos-master/apps/nethack/src/nethack-3.4.3/src/
H A Dsp_lev.c54 #define TOP 1 macro
484 case TOP:
2138 case TOP: ystart = 3; break;

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