Searched refs:PPTR_BASE (Results 1 - 14 of 14) sorted by relevance

/seL4-refos-master/kernel/include/plat/pc99/plat/32/plat_mode/machine/
H A Dhardware.h27 * +-------------------+ USER_TOP / PPTR_BASE / KERNEL_ELF_BASE
44 #define USER_TOP (PPTR_BASE & UL_CONST(0xFFC00000))
52 #define PPTR_BASE UL_CONST(0xe0000000) macro
80 #define KERNEL_ELF_BASE (PPTR_BASE + KERNEL_ELF_PADDR_BASE)
/seL4-refos-master/kernel/include/arch/arm/arch/64/mode/
H A Dhardware.h43 * +-----------------------------------+ <- PPTR_BASE: 256TiB minus 512GiB.
59 * 2^64 - 2^39 +-------------------+ PPTR_BASE
78 * 2^64 +-------------------+ PPTR_BASE
120 * 2^48 - 2^39 +-------------------+ PPTR_BASE
153 * 2^48 - 2^39 +-------------------+ PPTR_BASE |
176 #define PPTR_BASE UL_CONST(0x0000ff8000000000) macro
178 #define PPTR_BASE UL_CONST(0xffffff8000000000) macro
/seL4-refos-master/kernel/include/
H A Dhardware.h17 * - PPTR_BASE: The first virtual address of the kernel's physical
33 #define PPTR_BASE_OFFSET (PPTR_BASE - PADDR_BASE)
/seL4-refos-master/kernel/include/plat/pc99/plat/64/plat_mode/machine/
H A Dhardware.h15 * 2^64 - 2^39 +-------------------+ PPTR_BASE
53 * 2^64 - 2^39 +-------------------+ PPTR_BASE
77 #define PPTR_BASE UL_CONST(0xffffff8000000000) macro
81 #define TLBBITMAP_PPTR (PPTR_BASE - TLBBITMAP_PML4_RESERVED)
/seL4-refos-master/kernel/include/arch/arm/arch/32/mode/
H A Dhardware.h34 * +-------------------+ USER_TOP / PPTR_BASE / KERNEL_ELF_BASE
61 #define PPTR_BASE seL4_UserTop macro
/seL4-refos-master/kernel/include/arch/riscv/arch/64/mode/
H A Dhardware.h18 * kernel device mappings. This means that between PPTR_BASE and
42 * +-------------------PPTR_BASE-+ --+ 2^64 - 2^b
54 * | | | | | | PPTR_TOP - PPTR_BASE
86 #define PPTR_BASE UL_CONST(0xFFFFFFC000000000) macro
/seL4-refos-master/kernel/include/arch/riscv/arch/32/mode/
H A Dhardware.h22 * +-------------------+ USER_TOP / PPTR_BASE
38 #define PPTR_BASE seL4_UserTop macro
/seL4-refos-master/kernel/src/arch/x86/32/kernel/
H A Dvspace_32paging.c67 /* identity mapping from 0 up to PPTR_BASE (virtual address) */
68 for (i = 0; i < (PPTR_BASE >> seL4_LargePageBits); i++) {
84 /* mapping of PPTR_BASE (virtual address) to PADDR_BASE up to end of virtual address space */
85 for (i = 0; i < ((-PPTR_BASE) >> seL4_LargePageBits); i++) {
86 *(_boot_pd + i + (PPTR_BASE >> seL4_LargePageBits)) = pde_pde_large_new_phys(
192 for (i = PPTR_BASE >> seL4_LargePageBits; i < BIT(PD_INDEX_BITS); i++) {
H A Dvspace.c214 /* Mapping of PPTR_BASE (virtual address) to kernel's PADDR_BASE
218 idx = PPTR_BASE >> LARGE_PAGE_BITS;
340 unsigned int virt_pd_start = (PPTR_BASE >> LARGE_PAGE_BITS) - large_pages;
341 unsigned int virt_pg_start = PPTR_BASE - (large_pages << LARGE_PAGE_BITS);
/seL4-refos-master/kernel/src/arch/x86/64/kernel/
H A Dvspace.c56 assert(GET_PML4_INDEX(PPTR_BASE) == BIT(PML4_INDEX_BITS) - 1);
65 x64KSKernelPML4[GET_PML4_INDEX(PPTR_BASE)] = pml4e_new(
91 vaddr = PPTR_BASE;
140 assert(GET_PML4_INDEX(PPTR_BASE) == BIT(PML4_INDEX_BITS) - 1);
150 x64KSKernelPML4[GET_PML4_INDEX(PPTR_BASE)] = pml4e_new(
163 x64KSKernelPDPT[GET_PDPT_INDEX(PPTR_BASE) + pd_index] = pdpte_pdpte_pd_new(
187 vaddr = PPTR_BASE;
192 int pd_index = GET_PDPT_INDEX(vaddr) - GET_PDPT_INDEX(PPTR_BASE);
263 x64KSSKIMPML4[GET_PML4_INDEX(PPTR_BASE)] = pml4e_new(
755 * will be equivalent to copying from PPTR_BASE
[all...]
/seL4-refos-master/kernel/include/arch/x86/arch/64/mode/fastpath/
H A Dfastpath.h24 return unlikely(ret) ? TCB_PTR(ret | PPTR_BASE) : NULL;
/seL4-refos-master/kernel/src/arch/arm/64/kernel/
H A Dvspace.c244 assert(GET_PGD_INDEX(PPTR_BASE) == BIT(PGD_INDEX_BITS) - 1);
245 assert(IS_ALIGNED(PPTR_BASE, seL4_LargePageBits));
251 armKSGlobalKernelPGD[GET_PGD_INDEX(PPTR_BASE)] = pgde_pgde_pud_new(
255 for (idx = GET_PUD_INDEX(PPTR_BASE); idx < GET_PUD_INDEX(PPTR_TOP); idx++) {
262 vaddr = PPTR_BASE;
/seL4-refos-master/kernel/src/arch/arm/32/kernel/
H A Dvspace.c207 idx = PPTR_BASE >> pageBitsForSize(ARMSection);
334 /* mapping of PPTR_BASE (virtual address) to kernel's physBase */
594 lockTLBEntry(PPTR_BASE);
612 lockTLBEntry(PPTR_BASE);
1241 for (i = PPTR_BASE >> ARMSectionBits; i < BIT(PD_INDEX_BITS); i++) {
/seL4-refos-master/kernel/src/arch/riscv/kernel/
H A Dvspace.c112 /* kernel window starts at PPTR_BASE */
113 word_t pptr = PPTR_BASE;
351 for (i = RISCV_GET_PT_INDEX(PPTR_BASE, 0); i < BIT(PT_INDEX_BITS); i++) {

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