History log of /seL4-refos-master/kernel/src/arch/arm/32/kernel/vspace.c
Revision Date Author Comments
# a00c2c16 17-Sep-2020 Curtis Millar <curtis.millar@data61.csiro.au>

Make kernel log buffer derived from cmake config

This removes the explicit CMake configuration for the kernel log buffer
and replaces it with a #define that is enabled for the required
configurations.

Signed-off-by: Curtis Millar <curtis@curtism.me>


# 1a9756f6 09-Sep-2019 Qian Ge <qian.ge@data61.csiro.au>

SMMU: basic driver for init and probing

Introducing the driver in kernel for detecting SMMU features
and initialise the hardware.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>


# 4466c7c9 13-May-2020 Curtis Millar <curtis.millar@data61.csiro.au>

Remove references to kernelBase

kernelBase was used inconsistently between different architectures to
refer to the either of the first kernel address or the first address of
the mappings of the kernel ELF region specifically.

These have been replaced with more consistent use of constants
explicitly describing which region is being referenced.

Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>


# 79da0792 01-Mar-2020 Gerwin Klein <gerwin.klein@data61.csiro.au>

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.


# 531d6121 14-Oct-2019 Kent McLeod <Kent.Mcleod@data61.csiro.au>

arm: Restrict cache flush operations in hyp mode

Cache flush operations are applied through the kernel window mapping in
hyp mode. This requires an extra check that the frame being provided is
accessible through the kernel window.


# 0e62bc3a 01-Dec-2019 Victor Phan <Victor.Phan@data61.csiro.au>

Move vcpu_switch into Arch_switchToThread

Currently the vcpu_switch function is called in the setVMRoot function
after possible early returns. In order to make sure the vcpu is
always switched, the call is moved into Arch_switchToThread before the
call to setVMRoot.


# a4d6bf85 28-Feb-2016 amrzar <Amirreza.Zarrabi@data61.csiro.au>

SELFOUR-161: Merge Page_Remap with Page_Map

- Remove Remap function from seL4 API for arm, x86, riscv and the
respective invocation implementation.
- Update Map as replacement for Remap
- Update manual

This allows a change of rights if the frame being mapped is already
mapped in at the given vaddr. To map a page to a different address,
unmap it first.

Co-authored-by: Hesham Almatary <hesham.almatary@data61.csiro.au>
Co-authored-by: Anna Lyons <Anna.Lyons@data61.csiro.au>
Co-authored-by: Victor Phan <Victor.Phan@data61.csiro.au>
Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>


# fd83c0a3 20-Mar-2019 Curtis Millar <curtis.millar@data61.csiro.au>

Replace IPC_BUF_GLOBALS_FRAME with KERNEL_GLOBALS_FRAME

The globals frame no longer serves its original purpose of informing a
thread of its IPC buffer address, and instead as a virtual
implementation of thread ID registers.


# 8586b7f2 07-May-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

boot: refactor allocation of rootserver objects

Prior to this change, the boot process would dynamically allocate
memory for root server objects based on the order of initialisation.
Allocation was a best-fit algorithm.

This change preallocates all memory for root server objects to an
aligned untyped just after the user image. By allocating the objects in
order of size, allocation is greatly simplified and the ability to
reproduce the allocation offline based on the kernel and user image
sizes is increased.


# b2239d0d 07-Apr-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

boot: reduce duplicate code in map_kernel_frame

Reduce duplicated code by moving values that are different across
configs/attributes into their own conditionals, rather than the entire
call to pte_pte_small_new. This alters arm only.


# 7fc45c4e 18-Mar-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

style: set code width to 120


# 306453e3 18-Mar-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

style: set min-conditional-indent to 0

Given we use braces all the time conditional indents do not make code
cleaner.


# d0930f67 18-Mar-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

style: consistently attach return type

Add attach-return-type to astyle


# 761006e0 18-Mar-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

style: consistently align pointer with name

Run astyle with align-pointer=name


# 3d10ef0c 18-Mar-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

style: correct parenthesis padding

Use astyle's unpad-paren to unpad all parentheses that are not included
by pad-header, pad-oper, and pad-comma.


# fa017b6d 17-Mar-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

Upgrade to astyle 3.1

This produces minor changes


# eb857ec7 28-Jan-2019 Simon Shields <simon.shields@data61.csiro.au>

ARM: stop using plat/machine/devices.h

This header is going away and contains nothing of substance. Remove it.


# 3fc9ab0f 01-Jan-2019 Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au>

ARMv7: Fix cache and invalidation bugs in benchmark log setter

* Use cleanByVA_PoU since we are only cleaning a single word each iteration of the loop.
* invalidateTranslationSingle takes a virtual address, not a physical address


# d2644e8a 26-Oct-2017 Adrian Danis <Adrian.Danis@data61.csiro.au>

Declare and check IPC buffer size

Adds a named constant of the IPC buffer size bits that can be used when checking the
size/alignment of an IPC buffer. This constant has a compile time assertion to ensure
it corresponds to the actual IPC buffer


# 57fa0e0f 07-Aug-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

Share linker.h between architectures


# 0a6f9a5d 14-Mar-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

SELFOUR-748: ARM - Support local/remote TLB invalidation operations


# a8d52713 10-May-2017 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm: Do not print out message on failed lookup

This case can happen regularly in common kernel usage and this warning message
unnecessarily clutters output


# 9ca253a3 07-May-2017 Anna Lyons <Anna.Lyons@data61.csiro.au>

SELFOUR-879: expose index and entry constants


# 420ff03e 02-May-2017 Kent McLeod <Kent.Mcleod@data61.csiro.au>

SELFOUR-160: Add missing userError messages


# 3a64fa46 23-Apr-2017 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm: Correctly get base address of super sections in resolveVAddr


# c0a1dc75 20-Apr-2017 Rafal Kolanski <rafal.kolanski@nicta.com.au>

resolveVAddr: add default case to switch

Needed to make C parser happy.


# 982a1a04 20-Apr-2017 Bamboo <bamboo@keg.ertos.in.nicta.com.au>

[STYLE_FIX]


# c01bda56 20-Apr-2017 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm-hyp: Do not assume pages have valid mapping in resolveVAddr


# 85643b9f 20-Apr-2017 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm: Check type of all slots in large page mappings


# 701be5d0 19-Apr-2017 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm: Construct correct addresses for multi entry mappings when hyp enabled

Multi entry mappings (large pages and super sections) are a just a hint with the paging
format when hyp is enabled. As such the entry needs to be correct as though the hint bit
is not set, meaning each of the 16 entries needs to have an independently correct
address field. This was already done in the case of remapping, but not for mapping. This
change implements this for mapping, and changes the remapping code to use a loop
formulation that will be easier to verify.


# 0abc7202 04-Apr-2017 Adrian Danis <Adrian.Danis@data61.csiro.au>

s/DEBUG/CONFIG_DEBUG_BUILD/

DEBUG definition is not supposed to be used in the kernel, rather CONFIG_DEBUG_BUILD,
which can be toggled separately to user notion of DEBUG


# 3f90fad6 21-Mar-2017 Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au>

SELFOUR-836: Hardware debug API functions should take tcb_t and not arch_tcb_t

Touches files all throughout x86 (32 and 64) and ARM.


# de6d4772 30-Mar-2017 Rafal Kolanski <rafal.kolanski@nicta.com.au>

rename arch_tcb.vcpu -> arch_tcb.tcbVCPU, vcpu.tcb -> vcpu.vcpuTCB

struct vcpu { struct tcb* tcb; ...
struct arch_tcb { struct vcpu* vcpu; ...
and
struct tcb { struct arch_tcb tcbArch; ...

These conspire to generate a type error on verification side due to
assumptions about non-colliding names.


# 57336507 27-Mar-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

ARM/Hyp: vspace - enable nonexecutable (NX) attribute


# 4de4c5f6 13-Mar-2017 Kent McLeod <Kent.Mcleod@data61.csiro.au>

Add UNUSED


# a9f57e09 01-Mar-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

SELFOUR-744: ARM/SMP - Map kernel window and root task as cache-shareable

Default user PTEs/PDEs are also default to be shared. Later, we can
provide an option to allow the user not to map frames as shared.


# 712efa63 21-Feb-2017 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm_hyp: Use an explicitly invalid PD when there is no user one

When the user has no PD in order to schedule them we must still set something as
the active PD, just so that they can then fault. Previously when hypervisor was
enabled `0` was at as the PD. This worked as platforms typically do not have
anything valid, and certainly nothing resembling a page directory, at physical
address 0. This assumption is not very clean and unknown physical addresses
should not be accessed, so this change adds an explicit PD that is empty that
can be switched to.


# 48d17e1f 16-Jan-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

ARM/SMP: Prepare for ARM SMP adding stubs

Currently building ARM/SMP is broken. This commit:
1- Makes it possible to build ARM/SMP with stubs. Run-time SMP for ARM
DOES NOT WORK.
2- Can be a reference for future SMP targets to follow in order to
layout/add the minimal required files and functions needed to support SMP.
3- Builds for Sabre only. In order to support other platforms, ipi
interrupt ID should be defined in machine.h


# a3843293 19-Jan-2017 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm: SELFOUR-167: Use write allocate cache policy in kernel

Kernel currently uses a write back but not write allocate cache policy for kernel
memory mappings. This results in extremely poor performance for kernel operations
that need to zero memory that is not currently located in the cache. The change
in this commit is to use a write back and write allocate cache policy, matching
the policy used for user mappings


# 5d146463 18-Jan-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

ARM: Refactor how we get/set seL4 kernel stack

This commit makes seL4 hold the stack address on TPIDRPRW register (PL1 only
Thread ID Register, VMSA, see B4.1.150 section of ARMv7-A and ARMv7-R
edition reference manual).

Originally, the kernel stack was (re-)mapped to a fixed kernel virtual address and
on traps sp is loaded with this virtual address. Reason is to shave up some
cycles/instructions on (fast) traps path instead of having two instructions
(loading global variable pointer and then memory-load stack address from
it).

With ARM pipelining getting smart/complex (from ARMv7 onwards), there is
no noticeable difference in performance between the two implementations.
Furthermore, this change makes it easy for SMP to load different stacks
for each core and do CPU ID arithmetic efficiently. It also avoids the
issues involving (re-)mapping stacks for different cores if we
followed the original design.

Note: the main side-effect to this change is that the kernel stack for
ARM is no longer mapped with execute-never attribute.


# e9922b74 15-Jan-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

Unify kernel stack definition/declaration and share it between architecures/modes

Rather than defining a kernel stack in random places for each
architecure for each mode (32/64) and for single/SMP modes, make the
stack definition shareable between all of the above. This is also useful
for the future ARM SMP work.


# 60eef86c 14-Dec-2016 Hesham Almatary <hesham.almatary@data61.csiro.au>

Benchmark: Fix error due to fault function name change

s/fault_cap_fault_new/seL4_Fault_CapFault_new


# 2fea9a0f 18-Jul-2016 Anna Lyons <Anna.Lyons@nicta.com.au>

SELFOUR-567: use seL4_CapRights_t from libsel4

This change

* changes seL4_CapRights from the kernel to be seL4_CapRights_t in
libsel4
* deprecates the duplicated seL4_CapRights in libsel4, which is
now the bitfield generated type seL4_CapRights_t.
* fixes all usages in kernel and libsel4

Impact: for verification, this will require the type to change name
from cap_rights to seL4_CapRights_t.
This is a breaking libsel4 API change, although most code uses
seL4_AllRights or similar constants, which will not break
at a source level as these constants have been updated.


# b827ad37 15-Jul-2016 Anna Lyons <Anna.Lyons@nicta.com.au>

SELFOUR-413: refactor libsel4 fault API

This is a *breaking API change*

This commit:

* makes seL4_Fault_tag_t common between the kernel and libsel4
* deprecates the existing functions from sel4/messages.h includes
* introduces a new fault API in sel4/faults.h and
* sel4/sel4_arch/faults.h
* deprecates seL4_GetTag(), as the function did not work without
the user calling seL4_SetTag() first (seL4_MessageInfo is passed
in registers and not set in the IPC buffer)
* removes previously deprecated functions (deprecated prior to 3.0.0)
* updates the seL4 manual to reflect the changes


# 33a771d3 12-Jul-2016 Anna Lyons <Anna.Lyons@nicta.com.au>

Split fault types into arch/generic

Prior to this commit faults were separate
per architecture. This commit extracts the common
fault types and introduces arch specific faults,
reducing code duplication across architectures.


# e78cdf9b 27-Jul-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

SELFOUR-553: Support alternate IPC buffer locations without globals frame

This commit adds support for using the ThreadID registers of the ARM MPCore
platforms for storing the address of the IPC buffer instead of the globals
frame. The choice of using the user readable/writeable ThreadID register
is chosen, even though it means the user cannot use it for its own
purposes, as it leaves room in the future for doing TLS support in the
user read only register, where compilers expect it.


# 5f7fa2fc 19-Oct-2016 Hesham Almatary <hesham.almatary@data61.csiro.au>

Benchmark: Pack arch-independent benchmark-related files into separate directories


# fdad5085 13-Oct-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm_hyp: Move hype state into correct statedata header

The hypervisor state is declared in arch/32/statedata.c, but is
defined in arch/statedata.h. This commit moves the definitions to
arch/32/statedata.h to match all the other state in arch/32/statedata.c


# bebfcf6d 23-Jun-2016 Kofi Doku Atuah <kofi.dokuatuah@nicta.com.au>

SELFOUR-499: X86, ARM: Add userspace invocations for hardware debugging

This commit implements the body of SELFOUR-499. The API exposes the x86 DR0-7
and ARM coprocessor 14 features to userspace by virtualizing them as context-
switched registers in the TCB. Implemented as TCB invocations. This feature is
only built when CONFIG_HARDWARE_DEBUG_API is selected.

* Add low-level support routines for setting, unsetting, getting, enabling
and disabling breakpoints.
* Add support for single-stepping as well.
^ Single-stepping is not supported on ARMv6 since the hardware
doesn't have support.
^ ARM implements single-stepping as instruction breakpoints
configured to fault on every instruction -- this is achieved through
the "mismatch" mode, which is only supported from ARMv7 onwards.
* Also support explicit software break requests, a la "BKPT" and "INT $3".

* New invocations:
* seL4_TCB_SetBreakpoint().
* seL4_TCB_GetBreakpoint().
* seL4_TCB_UnsetBreakpoint().
* seL4_TCB_ConfigureSingleStepping().
* New constants:
^ Event types:
^ seL4_InstructionBreakpoint.
^ seL4_DataBreakpoint.
^ seL4_SoftwareBreakRequest.
^ Access types:
^ seL4_BreakOnRead.
^ seL4_BreakOnWrite.
^ seL4_BreakOnReadWrite.
^ Exports:
^ seL4_NumHWBreakpoints.
^ seL4_NumExclusiveBreakpoints.
^ seL4_NumExclusiveWatchpoints.
^ seL4_NumDualFunctionMonitors.
^ seL4_FirstBreakpoint.
^ seL4_FirstWatchpoint.
^ seL4_FirstDualFunctionMonitor.

See documentation in the seL4 API manual.


# bdd9beff 22-Sep-2016 Bamboo <bamboo@keg.ertos.in.nicta.com.au>

[STYLE_FIX]


# 59aa0ccd 30-Aug-2016 Xin,Gao <xin.gao@nicta.com.au>

SELFOUR-421: minor changes for c-refine


# d507b2d3 09-Feb-2016 Adrian Danis <Adrian.Danis@nicta.com.au>

SELFOUR-421 Introduce explicit device frames and untypeds

Kernel objects cannot be created from device untypeds, with the
exception of frames, which do not get zeroed and cannot be used
as an IPC buffer. Device untypeds additionally cannot be used
in the construction of ASID pools.

This then changes the API to the rootserver (i.e. bootinfo) to
send device untypeds instead of device frames. On ARM these
device untypeds are the same as the previously exported device
frame regions. On x86 PCI scanning is removed and all physical
memory addresses (that are not important for kernel integrity)
are released to the user.

In order to have bits in the frame and untyped caps on ARM the
number of software ASIDs had to be reduced from 2^18 to 2^17,
and the maximum untyped size reduced from 2^31 to 2^30


# 35c50cfd 29-Aug-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

SELFOUR-556: Rationalize BITS vs INDEX_BITS

s/PD_BITS/PD_INDEX_BITS
Current convention is to say that X_BITS is the log base 2
size of an object, not the log base 2 number of indices


# f251953f 29-Aug-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

SELFOUR-556: Rationalize BITS vs INDEX_BITS

s/PT_BITS/PT_INDEX_BITS
Current convention is to say that X_BITS is the log base 2
size of an object, not the log base 2 number of indices


# 16c34811 31-Jul-2016 Hesham Almatary <hesham.almatary@data61.csiro.au>

SELFOUR-518: User-level log buffer

Remove global ksLog and use KS_LOG_PPTR instead

Benchmark - Log buffer: use global page table


# 90628a75 11-Aug-2016 Hesham Almatary <hesham.almatary@data61.csiro.au>

Benchmark: share and use KS_LOG_PPTR and PPTR_TOP for x86 and ARM


# 2f163e27 11-Jul-2016 Hesham Almatary <hesham.almatary@data61.csiro.au>

astyle: Make comments compatible with both 2.03 and 2.04 astyle versions


# c50926b5 08-Jul-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

SELFOUR-559: Cleanup ARMPageUnmap for IO mappings

This commit moves setThreadState outside the 'perform' stage of the
invocation, and renames decodeARMIOUnmapInvocation to
performPageInvocationUnmapIO as it is actually doing a perform
and not a decode


# 5ca374b3 08-Jul-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

SELFOUR-558: Consistently name Unmap instead of UnMap


# 75299d05 08-Jul-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

SELFOUR-557: s/isIOSpaceFrame/isIOSpaceFrameCap/


# 09358f9b 23-Jun-2016 Hesham Almatary <Hesham.Almatary@nicta.com.au>

SELFOUR-448 Benchmark: Track thread's CPU utilisation time


# 5f7a1ef5 21-Jun-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm-hyp: Use BIT macro


# 08305335 21-Jun-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm-hyp: Add preprocessor guard comments


# bc3e62c8 20-Jun-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

trivial: style


# bae7367d 15-Jun-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm-hyp: Hide ARMPageMapIO invocation


# 785e2d7b 14-Jun-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm-hyp: Hide more calls to isIOSpaceFrame


# 6d6b047b 06-Jun-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

Minor fixes for other ARM platforms


# 5f0ae410 02-Jun-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

arm-hyp: Minor cleanups

Cleanup some small licensing, whitespace and configuration details


# 41603a26 01-Jun-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

Correct merge of master


# 7cbaeb8e 30-May-2016 Hesham Almatary <Hesham.Almatary@nicta.com.au>

SELFOUR-446 Benchmark: Track interrupts and user/vm faults


# bcb6dfd3 25-May-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

SELFOUR-208: Warn on downgraded write-only mappings


# fc1feb67 24-May-2016 Hesham Almatary <Hesham.Almatary@nicta.com.au>

SELFOUR-446 Benchmark: Track syscall feature

Benchmark feature that currently:
- Keeps track of system calls info
- Start time
- Duration
- Capability type
- Invocation tag
- Log the number of invocations of each system call*
- Log the number of invocations for each capability type per syscall.
- Has 3 new syscalls (dump, reset, get size).
- This new feature uses the existing log buffer (which is 1MiB for x86
and ARM). Since the number of syscall invocations is not
deterministic, the logged number of invocations is limited by the size
of the buffer. I suggested to enable the users to pass their own
user-level buffer, to enable more flexibility, later.
- ENABLE_BENCHMARKS is now a parent config option of trace points and
system call track features, they can't be used at the same time.


# 9aeee987 24-May-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

SELFOUR-449 Implement user stack trace on double fault


# 1287590e 16-May-2016 Adrian Danis <Adrian.Danis@data61.csiro.au>

Correct separation of printing and debug builds

Fixes some build issues with 541289a32603cee8242b5360b05e8f0c52795433
as well as further allowing debugging (via the capdl interface) to
happen when printing is turned off.


# 508e8747 16-May-2016 Yanyan Shen <yanyan.shen@nicta.com.au>

arm/tk1: connect objects with SMMU invocations


# 879d9724 13-May-2016 Yanyan Shen <yanyan.shen@nicta.com.au>

arm/tk1: a checkpoint for SMMU implementation


# 00538bb6 13-Mar-2016 Yanyan Shen <yanyan.shen@nicta.com.au>

arm/arm_hyp: remove #ifdef ARM_HYPs


# 96222bfc 13-Mar-2016 Yanyan Shen <yanyan.shen@nicta.com.au>

arm/arm_hyp: remove #ifdef ARM_HYPs


# 289bf92b 05-Jan-2016 Anna Lyons <Anna.Lyons@nicta.com.au>

SELFOUR-114: remove bootinfo.h duplication


# 69b7e077 25-Feb-2016 Yanyan Shen <yanyan.shen@nicta.com.au>

trivial: make style with astyle 2.03


# 9d12a096 25-Feb-2016 Yanyan Shen <yanyan.shen@nicta.com.au>

trivial: make style commit


# 6523fe40 21-Feb-2016 Adrian Danis <Adrian.Danis@nicta.com.au>

Correct previous merge


# cfcaf49c 31-Jan-2016 Adrian Danis <Adrian.Danis@nicta.com.au>

SELFOUR-399: object sizes and globals frame addr should come from the same source


# 9b7a8405 22-Jun-2015 Adrian Danis <Adrian.Danis@nicta.com.au>

Change bootinfo to have generic slot region for paging structures

Current bootinfo defines two slot regions for paging structures,
one for page directories and one for page tables. This does not
easily generalise for N levels of paging structures. This change
uses a single region that has a known order of objects for however
many levels exist


# 3959ced3 17-Jan-2016 amrzar <azarrabi@nicta.com.au>

Remove mode dependant codes for initial thread from architecture dependant boot codes


# 86942825 15-Jan-2016 amrzar <azarrabi@nicta.com.au>

Rearranging sources for aarch32 to 32/*