Searched refs:CLK_FPGA_PL2 (Results 1 - 4 of 4) sorted by relevance

/seL4-refos-master/libs/libplatsupport/plat_include/zynq7000/platsupport/plat/
H A Dclock.h47 CLK_FPGA_PL2, enumerator in enum:clk_id
/seL4-refos-master/projects/util_libs/libplatsupport/plat_include/zynq7000/platsupport/plat/
H A Dclock.h47 CLK_FPGA_PL2, enumerator in enum:clk_id
/seL4-refos-master/libs/libplatsupport/src/plat/zynq7000/
H A Dclock.c892 case CLK_FPGA_PL2:
1035 [CLK_FPGA_PL2] = &fpga_pl2_clk,
1067 [CLK_FPGA_PL2] = 50 * MHZ,
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/zynq7000/
H A Dclock.c892 case CLK_FPGA_PL2:
1035 [CLK_FPGA_PL2] = &fpga_pl2_clk,
1067 [CLK_FPGA_PL2] = 50 * MHZ,

Completed in 87 milliseconds