Searched refs:CLK_DDR_PLL (Results 1 - 4 of 4) sorted by relevance
| /seL4-refos-master/libs/libplatsupport/plat_include/zynq7000/platsupport/plat/ |
| H A D | clock.h | 19 CLK_DDR_PLL, enumerator in enum:clk_id
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| /seL4-refos-master/projects/util_libs/libplatsupport/plat_include/zynq7000/platsupport/plat/ |
| H A D | clock.h | 19 CLK_DDR_PLL, enumerator in enum:clk_id
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| /seL4-refos-master/libs/libplatsupport/src/plat/zynq7000/ |
| H A D | clock.c | 296 CLK_DDR_PLL,
304 CLK_DDR_PLL
432 case CLK_DDR_PLL:
722 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_DDR_PLL);
1010 [CLK_DDR_PLL] = &ddr_pll_clk,
1042 [CLK_DDR_PLL] = 1067 * MHZ,
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| /seL4-refos-master/projects/util_libs/libplatsupport/src/plat/zynq7000/ |
| H A D | clock.c | 296 CLK_DDR_PLL,
304 CLK_DDR_PLL
432 case CLK_DDR_PLL:
722 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_DDR_PLL);
1010 [CLK_DDR_PLL] = &ddr_pll_clk,
1042 [CLK_DDR_PLL] = 1067 * MHZ,
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