/seL4-l4v-master/l4v/spec/haskell/include/ |
H A D | gic.h | 10 uint32_t enable; /* 0x000 */ 11 uint32_t ic_type; /* 0x004 */ 12 uint32_t dist_ident; /* 0x008 */ 13 uint32_t res1[29]; /* [0x00C, 0x080) */ 15 uint32_t security[32]; /* [0x080, 0x100) */ 17 uint32_t enable_set[32]; /* [0x100, 0x180) */ 18 uint32_t enable_clr[32]; /* [0x180, 0x200) */ 19 uint32_t pending_set[32]; /* [0x200, 0x280) */ 20 uint32_t pending_clr[32]; /* [0x280, 0x300) */ 21 uint32_t activ [all...] |
H A D | mct.h | 10 uint32_t reserved0[64]; 11 uint32_t cntl; /* 0x100 Low word of count */ 12 uint32_t cnth; /* 0x104 High word of count */ 13 uint32_t reserved1[1]; 14 uint32_t cnt_wstat; /* 0x110 Write status for cnt */ 15 uint32_t reserved2[60]; 17 uint32_t comp0l; /* 0x200 Low word of Compare value */ 18 uint32_t comp0h; /* 0x204 High word of Compare value*/ 19 uint32_t comp0_add_inc; /* 0x208 Low word of Automatic increment amount */ 20 uint32_t comp0_re [all...] |
H A D | mptimer.h | 10 uint32_t load; 11 uint32_t count; 12 uint32_t ctrl; 13 uint32_t ints;
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/seL4-l4v-master/seL4/include/plat/tk1/plat/machine/ |
H A D | smmu.h | 21 uint32_t intstatus; /* 0x00 */ 22 uint32_t intmask; /* 0x04 */ 23 uint32_t err_status; /* 0x08 */ 24 uint32_t err_adr; /* 0x0c */ 25 uint32_t smmu_config; /* 0x10 */ 26 uint32_t smmu_tlb_config; /* 0x14 */ 27 uint32_t smmu_ptc_config; /* 0x18 */ 28 uint32_t smmu_ptb_asid; /* 0x1c */ 29 uint32_t smmu_ptb_data; /* 0x20 */ 30 uint32_t reserved [all...] |
/seL4-l4v-master/seL4/include/drivers/timer/ |
H A D | imx31-epit.h | 11 uint32_t epitcr; 12 uint32_t epitsr; 13 uint32_t epitlr; 14 uint32_t epitcmpr; 15 uint32_t epitcnt;
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H A D | arm_priv.h | 13 uint32_t load; 14 uint32_t count; 15 uint32_t ctrl; 16 uint32_t ints;
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H A D | allwinner.h | 12 uint32_t tmr_irq_en_reg; /* Timer IRQ Enable Register 0x00 */ 13 uint32_t tmr_irq_sta_reg; /* Timer Status Register 0x04 */ 14 uint32_t tmr_reserved01[2]; 15 uint32_t tmr0_ctrl_reg; /* Timer 0 Control Register 0x10 */ 16 uint32_t tmr0_intv_value_reg; /* Timer 0 Interval Value Register 0x14 */ 17 uint32_t tmr0_cur_value_reg; /* Timer 0 Current Value Register 0x18 */
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H A D | omap3430.h | 15 uint32_t tidr; /* GPTIMER_TIDR 0x00 */ 16 uint32_t padding1[3]; 17 uint32_t cfg; /* GPTIMER_CFG 0x10 */ 18 uint32_t tistat; /* GPTIMER_TISTAT 0x14 */ 19 uint32_t tisr; /* GPTIMER_TISR 0x18 */ 20 uint32_t tier; /* GPTIMER_TIER 0x1C */ 21 uint32_t twer; /* GPTIMER_TWER 0x20 */ 22 uint32_t tclr; /* GPTIMER_TCLR 0x24 */ 23 uint32_t tcrr; /* GPTIMER_TCRR 0x28 */ 24 uint32_t tld [all...] |
H A D | mct.h | 61 uint32_t reserved0[64]; 62 uint32_t cntl; /* 0x100 Low word of count */ 63 uint32_t cnth; /* 0x104 High word of count */ 64 uint32_t reserved1[1]; 65 uint32_t cnt_wstat; /* 0x110 Write status for cnt */ 66 uint32_t reserved2[60]; 68 uint32_t comp0l; /* 0x200 Low word of Compare value */ 69 uint32_t comp0h; /* 0x204 High word of Compare value*/ 70 uint32_t comp0_add_inc; /* 0x208 Low word of Automatic increment amount */ 71 uint32_t comp0_re [all...] |
H A D | am335x.h | 15 uint32_t tidr; // 00h TIDR Identification Register 16 uint32_t padding1[3]; 17 uint32_t cfg; // 10h TIOCP_CFG Timer OCP Configuration Register 18 uint32_t padding2[3]; 19 uint32_t tieoi; // 20h IRQ_EOI Timer IRQ End-Of-Interrupt Register 20 uint32_t tisrr; // 24h IRQSTATUS_RAW Timer IRQSTATUS Raw Register 21 uint32_t tisr; // 28h IRQSTATUS Timer IRQSTATUS Register 22 uint32_t tier; // 2Ch IRQSTATUS_SET Timer IRQENABLE Set Register 23 uint32_t ticr; // 30h IRQSTATUS_CLR Timer IRQENABLE Clear Register 24 uint32_t twe [all...] |
H A D | imx31-gpt.h | 21 uint32_t gptcr; /* control */ 22 uint32_t gptpr; /* prescaler */ 23 uint32_t gptsr; /* status register */ 24 uint32_t gptir; /* interrupt register */ 25 uint32_t gptcr1; 26 uint32_t gptcr2; 27 uint32_t gptcr3; 28 uint32_t gpticr1; 29 uint32_t gpticr2; 30 uint32_t gptcn [all...] |
/seL4-l4v-master/seL4/include/arch/x86/arch/32/mode/kernel/ |
H A D | elf.h | 18 uint32_t e_version; /* Elf version (should be 1) */ 19 uint32_t e_entry; /* Code entry point */ 20 uint32_t e_phoff; /* Program header table */ 21 uint32_t e_shoff; /* Section header table */ 22 uint32_t e_flags; /* Flags */ 33 uint32_t p_type; /* Segment type: Loadable segment = 1 */ 34 uint32_t p_offset; /* Offset of segment in file */ 35 uint32_t p_vaddr; /* Reqd virtual address of segment when loading */ 36 uint32_t p_paddr; /* Reqd physical address of segment (ignore) */ 37 uint32_t p_files [all...] |
/seL4-l4v-master/seL4/include/arch/x86/arch/kernel/ |
H A D | multiboot.h | 17 uint32_t start; 18 uint32_t end; 19 uint32_t name; 20 uint32_t reserved; 24 uint32_t size; 27 uint32_t type; 33 uint32_t flags; 34 uint32_t mem_lower; 35 uint32_t mem_upper; 36 uint32_t boot_devic [all...] |
H A D | multiboot2.h | 14 uint32_t total_size; 15 uint32_t unknown; 19 uint32_t type; 20 uint32_t size; 26 uint32_t type; 27 uint32_t reserved; 31 uint32_t start; 32 uint32_t end; 38 uint32_t pitch; 39 uint32_t widt [all...] |
/seL4-l4v-master/seL4/include/drivers/irq/ |
H A D | imx31.h | 19 uint32_t intctl; 20 uint32_t nimask; 21 uint32_t intennum; 22 uint32_t intdisnum; 23 uint32_t intenableh; 24 uint32_t intenablel; 25 uint32_t inttypeh; 26 uint32_t inttypel; 27 uint32_t nipriority[8]; 28 uint32_t nivecs [all...] |
H A D | am335x.h | 18 #define CMPER_REG(base, off) ((volatile uint32_t *)((base) + (off))) 41 uint32_t padding[4]; 42 uint32_t intcps_sysconfig; 43 uint32_t intcps_sysstatus; 44 uint32_t padding2[10]; 45 uint32_t intcps_sir_irq; 46 uint32_t intcps_sir_fiq; 47 uint32_t intcps_control; 48 uint32_t intcps_protection; 49 uint32_t intcps_idl [all...] |
H A D | omap3.h | 29 uint32_t padding[4]; 30 uint32_t intcps_sysconfig; 31 uint32_t intcps_sysstatus; 32 uint32_t padding2[10]; 33 uint32_t intcps_sir_irq; 34 uint32_t intcps_sir_fiq; 35 uint32_t intcps_control; 36 uint32_t intcps_protection; 37 uint32_t intcps_idle; 38 uint32_t padding [all...] |
H A D | bcm2836-armctrl-ic.h | 83 uint32_t bfIRQBasicPending; /* 0x200 R */ 84 uint32_t bfGPUIRQPending[2]; /* 0x204 R */ 85 uint32_t FIQ_control; /* 0x20C R/W */ 86 uint32_t bfEnableIRQs[2]; /* 0x210 R/Wbs */ 87 uint32_t bfEnableBasicIRQs; /* 0x218 R/Wbs */ 88 uint32_t bfDisableIRQs[2]; /* 0x21C R/Wbc */ 89 uint32_t bfDisableBasicIRQs; /* 0x224 R/Wbc */ 93 uint32_t controlRegister; /* 0x00 */ 94 uint32_t unused0; /* 0x04 */ 95 uint32_t coreTimerPrescale [all...] |
/seL4-l4v-master/seL4/include/arch/arm/arch/machine/ |
H A D | gic_v2.h | 49 uint32_t enable; /* 0x000 */ 50 uint32_t ic_type; /* 0x004 */ 51 uint32_t dist_ident; /* 0x008 */ 52 uint32_t res1[29]; /* [0x00C, 0x080) */ 54 uint32_t security[32]; /* [0x080, 0x100) */ 56 uint32_t enable_set[32]; /* [0x100, 0x180) */ 57 uint32_t enable_clr[32]; /* [0x180, 0x200) */ 58 uint32_t pending_set[32]; /* [0x200, 0x280) */ 59 uint32_t pending_clr[32]; /* [0x280, 0x300) */ 60 uint32_t activ [all...] |
H A D | gic_v3.h | 78 uint32_t ctlr; /* 0x0000 */ 79 uint32_t typer; /* 0x0004 */ 80 uint32_t iidr; /* 0x0008 */ 81 uint32_t res0; /* 0x000C */ 82 uint32_t statusr; /* 0x0010 */ 83 uint32_t res1[11]; /* [0x0014, 0x0040) */ 84 uint32_t setspi_nsr; /* 0x0040 */ 85 uint32_t res2; /* 0x0044 */ 86 uint32_t clrspi_nsr; /* 0x0048 */ 87 uint32_t res [all...] |
/seL4-l4v-master/l4v/tools/autocorres/tests/proof-tests/ |
H A D | word_abs_fn_call.c | 8 typedef unsigned int uint32_t; typedef 10 uint8_t foo(int a, uint32_t b, uint8_t c) 15 uint8_t bar(int a, uint32_t b, uint8_t c) 20 uint32_t foo2(int a, uint32_t b, uint8_t c) 25 uint32_t bar2(int a, uint32_t b, uint8_t c) 30 uint8_t foo3(int a, uint32_t b, uint8_t c) 35 uint8_t bar3(int a, uint32_t b, uint8_t c) 40 uint32_t foo [all...] |
/seL4-l4v-master/seL4/include/arch/arm/arch/32/mode/ |
H A D | types.h | 12 typedef uint32_t timestamp_t;
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/seL4-l4v-master/seL4/src/arch/arm/machine/ |
H A D | l2c_310.c | 104 uint32_t cache_id; /* 0x000 */ 105 uint32_t cache_type; /* 0x004 */ 106 uint32_t res[62]; 110 uint32_t control; /* 0x100 */ 111 uint32_t aux_control; /* 0x104 */ 112 uint32_t tag_ram_control; /* 0x108 */ 113 uint32_t data_ram_control; /* 0x10C */ 114 uint32_t res[60]; 118 uint32_t ev_counter_ctrl; /* 0x200 */ 119 uint32_t ev_counter1_cf [all...] |
/seL4-l4v-master/seL4/src/plat/imx31/machine/ |
H A D | hardware.c | 25 uint32_t id; /* 000 */ 26 uint32_t type; /* 004 */ 32 uint32_t control; /* 100 */ 33 uint32_t aux_control; /* 104 */ 39 uint32_t pad_0[12]; 40 uint32_t sync; /* 730 */ 41 uint32_t pad_1[15]; 42 uint32_t inv_by_pa; /* 770 */ 43 uint32_t pad_2[2]; 44 uint32_t inv_by_wa [all...] |
/seL4-l4v-master/l4v/tools/c-parser/testfiles/ |
H A D | bug_mvt20110302.c | 7 typedef unsigned long uint32_t; typedef 8 typedef uint32_t vptr_t; 11 uint32_t words[2]; 16 uint32_t words[2];
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