1/*
2 * Copyright 2014, General Dynamics C4 Systems
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 */
6
7#include <stdint.h>
8/* Memory map for GIC distributor */
9typedef struct gic_dist_map_t {
10    uint32_t enable;                /* 0x000 */
11    uint32_t ic_type;               /* 0x004 */
12    uint32_t dist_ident;            /* 0x008 */
13    uint32_t res1[29];              /* [0x00C, 0x080) */
14
15    uint32_t security[32];          /* [0x080, 0x100) */
16
17    uint32_t enable_set[32];        /* [0x100, 0x180) */
18    uint32_t enable_clr[32];        /* [0x180, 0x200) */
19    uint32_t pending_set[32];       /* [0x200, 0x280) */
20    uint32_t pending_clr[32];       /* [0x280, 0x300) */
21    uint32_t active[32];            /* [0x300, 0x380) */
22    uint32_t res2[32];              /* [0x380, 0x400) */
23
24    uint32_t priority[255];         /* [0x400, 0x7FC) */
25    uint32_t res3;                  /* 0x7FC */
26
27    uint32_t targets[255];            /* [0x800, 0xBFC) */
28    uint32_t res4;                  /* 0xBFC */
29
30    uint32_t config[64];             /* [0xC00, 0xD00) */
31
32    uint32_t spi[32];               /* [0xD00, 0xD80) */
33    uint32_t res5[20];              /* [0xD80, 0xDD0) */
34    uint32_t res6;                  /* 0xDD0 */
35    uint32_t legacy_int;            /* 0xDD4 */
36    uint32_t res7[2];               /* [0xDD8, 0xDE0) */
37    uint32_t match_d;               /* 0xDE0 */
38    uint32_t enable_d;              /* 0xDE4 */
39    uint32_t res8[70];               /* [0xDE8, 0xF00) */
40
41    uint32_t sgi_control;           /* 0xF00 */
42    uint32_t res9[3];               /* [0xF04, 0xF10) */
43    uint32_t sgi_pending_clr[4];    /* [0xF10, 0xF20) */
44    uint32_t res10[40];             /* [0xF20, 0xFC0) */
45
46    uint32_t periph_id[12];         /* [0xFC0, 0xFF0) */
47    uint32_t component_id[4];       /* [0xFF0, 0xFFF] */
48} gic_dist_map;
49
50/* Memory map for GIC  cpu interface */
51typedef struct gic_cpu_iface_map {
52    uint32_t icontrol;              /*  0x000         */
53    uint32_t pri_msk_c;             /*  0x004         */
54    uint32_t pb_c;                  /*  0x008         */
55    uint32_t int_ack;               /*  0x00C         */
56    uint32_t eoi;                   /*  0x010         */
57    uint32_t run_priority;          /*  0x014         */
58    uint32_t hi_pend;               /*  0x018         */
59    uint32_t ns_alias_bp_c;         /*  0x01C         */
60    uint32_t ns_alias_ack;          /*  0x020 GIC400 only */
61    uint32_t ns_alias_eoi;          /*  0x024 GIC400 only */
62    uint32_t ns_alias_hi_pend;      /*  0x028 GIC400 only */
63
64    uint32_t res1[5];               /* [0x02C, 0x040) */
65
66    uint32_t integ_en_c;            /*  0x040 PL390 only */
67    uint32_t interrupt_out;         /*  0x044 PL390 only */
68    uint32_t res2[2];               /* [0x048, 0x050)    */
69
70    uint32_t match_c;               /*  0x050 PL390 only */
71    uint32_t enable_c;              /*  0x054 PL390 only */
72
73    uint32_t res3[30];              /* [0x058, 0x0FC)  */
74    uint32_t active_priority[4];    /* [0x0D0, 0xDC] GIC400 only */
75    uint32_t ns_active_priority[4]; /* [0xE0,0xEC] GIC400 only */
76    uint32_t res4[3];
77
78    uint32_t cpu_if_ident;          /*  0x0FC         */
79    uint32_t res5[948];             /* [0x100. 0xFC0) */
80
81    uint32_t periph_id[8];          /* [0xFC0, 9xFF0) PL390 only */
82    uint32_t component_id[4];       /* [0xFF0, 0xFFF] PL390 only */
83} gic_cpu_iface_map;
84
85