Searched refs:seL4_LargePageBits (Results 1 - 20 of 20) sorted by relevance

/seL4-l4v-master/seL4/include/plat/pc99/plat/32/plat_mode/machine/
H A Dhardware.h60 #define TLBBITMAP_PD_RESERVED (TLBBITMAP_ROOT_ENTRIES * BIT(seL4_LargePageBits))
64 #define LOGBUFFER_PD_RESERVED BIT(seL4_LargePageBits)
/seL4-l4v-master/seL4/include/arch/x86/arch/machine/
H A Dhardware.h16 #define LARGE_PAGE_BITS seL4_LargePageBits
36 X64LargePageBits = seL4_LargePageBits,
61 return seL4_LargePageBits;
83 return seL4_LargePageBits;
/seL4-l4v-master/seL4/include/arch/arm/arch/64/mode/machine/
H A Dhardware.h37 ARMLargePageBits = seL4_LargePageBits,
/seL4-l4v-master/seL4/libsel4/sel4_arch_include/ia32/sel4/sel4_arch/
H A Dconstants.h50 #define seL4_LargePageBits 22 /* 4MB */ macro
60 #define seL4_4MBits seL4_LargePageBits
/seL4-l4v-master/seL4/src/arch/x86/32/kernel/
H A Dvspace_32paging.c68 for (i = 0; i < (PPTR_BASE >> seL4_LargePageBits); i++) {
70 i << seL4_LargePageBits, /* physical address */
85 for (i = 0; i < ((-PPTR_BASE) >> seL4_LargePageBits); i++) {
86 *(_boot_pd + i + (PPTR_BASE >> seL4_LargePageBits)) = pde_pde_large_new_phys(
87 (i << seL4_LargePageBits) + PADDR_BASE, /* physical address */
109 *(pd + (vptr >> seL4_LargePageBits)) = pde_pde_pt_new(
136 pd += (vptr >> seL4_LargePageBits);
138 *(pt + ((vptr & MASK(seL4_LargePageBits)) >> seL4_PageBits)) = pte_new(
192 for (i = PPTR_BASE >> seL4_LargePageBits; i < BIT(PD_INDEX_BITS); i++) {
331 offset = vaddr & MASK(seL4_LargePageBits);
[all...]
/seL4-l4v-master/seL4/include/plat/pc99/plat/64/plat_mode/machine/
H A Dhardware.h104 #define KS_LOG_PPTR (KDEV_BASE + BIT(seL4_LargePageBits))
/seL4-l4v-master/seL4/include/arch/arm/arch/32/mode/machine/
H A Dhardware.h110 ARMLargePageBits = seL4_LargePageBits,
/seL4-l4v-master/seL4/include/arch/riscv/arch/machine/
H A Dhardware.h78 RISCVMegaPageBits = seL4_LargePageBits,
/seL4-l4v-master/seL4/libsel4/sel4_arch_include/riscv64/sel4/sel4_arch/
H A Dconstants.h38 #define seL4_LargePageBits 21 macro
/seL4-l4v-master/seL4/libsel4/sel4_arch_include/riscv32/sel4/sel4_arch/
H A Dconstants.h38 #define seL4_LargePageBits 22 macro
/seL4-l4v-master/seL4/libsel4/sel4_arch_include/x86_64/sel4/sel4_arch/
H A Dconstants.h56 #define seL4_LargePageBits 21 macro
/seL4-l4v-master/seL4/libsel4/sel4_arch_include/arm_hyp/sel4/sel4_arch/
H A Dconstants.h168 #define seL4_LargePageBits 16 macro
/seL4-l4v-master/seL4/libsel4/sel4_arch_include/aarch32/sel4/sel4_arch/
H A Dconstants.h168 #define seL4_LargePageBits 16 macro
/seL4-l4v-master/seL4/libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/
H A Dconstants.h175 #define seL4_LargePageBits 21 macro
/seL4-l4v-master/seL4/src/arch/riscv/machine/
H A Dhardware.c63 .end = kernel_devices[i].paddr + (1 << seL4_LargePageBits),
/seL4-l4v-master/seL4/src/arch/riscv/object/
H A Dobjecttype.c179 return seL4_LargePageBits;
/seL4-l4v-master/seL4/src/arch/x86/64/machine/
H A Dcapdl.c85 case seL4_LargePageBits:
125 page_size = seL4_LargePageBits;
/seL4-l4v-master/seL4/src/arch/x86/64/kernel/
H A Dvspace.c285 assert((skim_start % BIT(seL4_LargePageBits)) == 0);
286 assert((skim_end % BIT(seL4_LargePageBits)) == 0);
302 paddr += BIT(seL4_LargePageBits);
1565 offset = vaddr & MASK(seL4_LargePageBits);
/seL4-l4v-master/seL4/src/arch/arm/64/kernel/
H A Dvspace.c245 assert(IS_ALIGNED(PPTR_BASE, seL4_LargePageBits));
263 for (paddr = PADDR_BASE; paddr < PADDR_TOP; paddr += BIT(seL4_LargePageBits)) {
277 vaddr += BIT(seL4_LargePageBits);
/seL4-l4v-master/seL4/src/arch/riscv/kernel/
H A Dvspace.c1225 assert(physical_address - ksUserLogBuffer == BIT(seL4_LargePageBits));

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