/seL4-l4v-10.1.1/l4v/spec/haskell/include/ |
H A D | gic.h | 14 uint32_t enable; /* 0x000 */ 15 uint32_t ic_type; /* 0x004 */ 16 uint32_t dist_ident; /* 0x008 */ 17 uint32_t res1[29]; /* [0x00C, 0x080) */ 19 uint32_t security[32]; /* [0x080, 0x100) */ 21 uint32_t enable_set[32]; /* [0x100, 0x180) */ 22 uint32_t enable_clr[32]; /* [0x180, 0x200) */ 23 uint32_t pending_set[32]; /* [0x200, 0x280) */ 24 uint32_t pending_clr[32]; /* [0x280, 0x300) */ 25 uint32_t activ [all...] |
H A D | mct.h | 14 uint32_t reserved0[64]; 15 uint32_t cntl; /* 0x100 Low word of count */ 16 uint32_t cnth; /* 0x104 High word of count */ 17 uint32_t reserved1[1]; 18 uint32_t cnt_wstat; /* 0x110 Write status for cnt */ 19 uint32_t reserved2[60]; 21 uint32_t comp0l; /* 0x200 Low word of Compare value */ 22 uint32_t comp0h; /* 0x204 High word of Compare value*/ 23 uint32_t comp0_add_inc; /* 0x208 Low word of Automatic increment amount */ 24 uint32_t comp0_re [all...] |
H A D | mptimer.h | 14 uint32_t load; 15 uint32_t count; 16 uint32_t ctrl; 17 uint32_t ints;
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/seL4-l4v-10.1.1/seL4/include/plat/tk1/plat/machine/ |
H A D | smmu.h | 26 uint32_t intstatus; /* 0x00 */ 27 uint32_t intmask; /* 0x04 */ 28 uint32_t err_status; /* 0x08 */ 29 uint32_t err_adr; /* 0x0c */ 30 uint32_t smmu_config; /* 0x10 */ 31 uint32_t smmu_tlb_config; /* 0x14 */ 32 uint32_t smmu_ptc_config; /* 0x18 */ 33 uint32_t smmu_ptb_asid; /* 0x1c */ 34 uint32_t smmu_ptb_data; /* 0x20 */ 35 uint32_t reserved [all...] |
/seL4-l4v-10.1.1/seL4/include/plat/omap3/plat/machine/ |
H A D | timer.h | 22 uint32_t tidr; /* GPTIMER_TIDR 0x00 */ 23 uint32_t padding1[3]; 24 uint32_t cfg; /* GPTIMER_CFG 0x10 */ 25 uint32_t tistat; /* GPTIMER_TISTAT 0x14 */ 26 uint32_t tisr; /* GPTIMER_TISR 0x18 */ 27 uint32_t tier; /* GPTIMER_TIER 0x1C */ 28 uint32_t twer; /* GPTIMER_TWER 0x20 */ 29 uint32_t tclr; /* GPTIMER_TCLR 0x24 */ 30 uint32_t tcrr; /* GPTIMER_TCRR 0x28 */ 31 uint32_t tld [all...] |
H A D | interrupt.h | 29 uint32_t padding[4]; 30 uint32_t intcps_sysconfig; 31 uint32_t intcps_sysstatus; 32 uint32_t padding2[10]; 33 uint32_t intcps_sir_irq; 34 uint32_t intcps_sir_fiq; 35 uint32_t intcps_control; 36 uint32_t intcps_protection; 37 uint32_t intcps_idle; 38 uint32_t padding [all...] |
/seL4-l4v-10.1.1/seL4/include/plat/am335x/plat/machine/ |
H A D | timer.h | 23 uint32_t tidr; // 00h TIDR Identification Register 24 uint32_t padding1[3]; 25 uint32_t cfg; // 10h TIOCP_CFG Timer OCP Configuration Register 26 uint32_t padding2[3]; 27 uint32_t tieoi; // 20h IRQ_EOI Timer IRQ End-Of-Interrupt Register 28 uint32_t tisrr; // 24h IRQSTATUS_RAW Timer IRQSTATUS Raw Register 29 uint32_t tisr; // 28h IRQSTATUS Timer IRQSTATUS Register 30 uint32_t tier; // 2Ch IRQSTATUS_SET Timer IRQENABLE Set Register 31 uint32_t ticr; // 30h IRQSTATUS_CLR Timer IRQENABLE Clear Register 32 uint32_t twe [all...] |
H A D | interrupt.h | 23 #define CMPER_REG(base, off) ((volatile uint32_t *)((base) + (off))) 41 uint32_t padding[4]; 42 uint32_t intcps_sysconfig; 43 uint32_t intcps_sysstatus; 44 uint32_t padding2[10]; 45 uint32_t intcps_sir_irq; 46 uint32_t intcps_sir_fiq; 47 uint32_t intcps_control; 48 uint32_t intcps_protection; 49 uint32_t intcps_idl [all...] |
/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/32/mode/kernel/ |
H A D | elf.h | 24 uint32_t e_version; /* Elf version (should be 1) */ 25 uint32_t e_entry; /* Code entry point */ 26 uint32_t e_phoff; /* Program header table */ 27 uint32_t e_shoff; /* Section header table */ 28 uint32_t e_flags; /* Flags */ 39 uint32_t p_type; /* Segment type: Loadable segment = 1 */ 40 uint32_t p_offset; /* Offset of segment in file */ 41 uint32_t p_vaddr; /* Reqd virtual address of segment when loading */ 42 uint32_t p_paddr; /* Reqd physical address of segment (ignore) */ 43 uint32_t p_files [all...] |
/seL4-l4v-10.1.1/seL4/include/plat/allwinnerA20/plat/machine/ |
H A D | timer.h | 20 uint32_t tmr_irq_en_reg; /* Timer IRQ Enable Register 0x00 */ 21 uint32_t tmr_irq_sta_reg; /* Timer Status Register 0x04 */ 22 uint32_t tmr_reserved01[2]; 23 uint32_t tmr0_ctrl_reg; /* Timer 0 Control Register 0x10 */ 24 uint32_t tmr0_intv_value_reg; /* Timer 0 Interval Value Register 0x14 */ 25 uint32_t tmr0_cur_value_reg; /* Timer 0 Current Value Register 0x18 */
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/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/kernel/ |
H A D | multiboot.h | 23 uint32_t start; 24 uint32_t end; 25 uint32_t name; 26 uint32_t reserved; 30 uint32_t size; 33 uint32_t type; 39 uint32_t flags; 40 uint32_t mem_lower; 41 uint32_t mem_upper; 42 uint32_t boot_devic [all...] |
H A D | multiboot2.h | 19 uint32_t total_size; 20 uint32_t unknown; 24 uint32_t type; 25 uint32_t size; 31 uint32_t type; 32 uint32_t reserved; 36 uint32_t start; 37 uint32_t end; 43 uint32_t pitch; 44 uint32_t widt [all...] |
/seL4-l4v-10.1.1/seL4/include/plat/imx31/plat/machine/ |
H A D | devices.h | 33 uint32_t id; /* 000 */ 34 uint32_t type; /* 004 */ 40 uint32_t control; /* 100 */ 41 uint32_t aux_control; /* 104 */ 47 uint32_t pad_0[12]; 48 uint32_t sync; /* 730 */ 49 uint32_t pad_1[15]; 50 uint32_t inv_by_pa; /* 770 */ 51 uint32_t pad_2[2]; 52 uint32_t inv_by_wa [all...] |
H A D | interrupt.h | 21 uint32_t intctl; 22 uint32_t nimask; 23 uint32_t intennum; 24 uint32_t intdisnum; 25 uint32_t intenableh; 26 uint32_t intenablel; 27 uint32_t inttypeh; 28 uint32_t inttypel; 29 uint32_t nipriority[8]; 30 uint32_t nivecs [all...] |
H A D | timer.h | 20 uint32_t epitcr; 21 uint32_t epitsr; 22 uint32_t epitlr; 23 uint32_t epitcmpr; 24 uint32_t epitcnt;
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/seL4-l4v-10.1.1/seL4/include/plat/exynos_common/plat/machine/ |
H A D | mct.h | 65 uint32_t reserved0[64]; 66 uint32_t cntl; /* 0x100 Low word of count */ 67 uint32_t cnth; /* 0x104 High word of count */ 68 uint32_t reserved1[1]; 69 uint32_t cnt_wstat; /* 0x110 Write status for cnt */ 70 uint32_t reserved2[60]; 72 uint32_t comp0l; /* 0x200 Low word of Compare value */ 73 uint32_t comp0h; /* 0x204 High word of Compare value*/ 74 uint32_t comp0_add_inc; /* 0x208 Low word of Automatic increment amount */ 75 uint32_t comp0_re [all...] |
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/machine/ |
H A D | gic_pl390.h | 67 uint32_t enable; /* 0x000 */ 68 uint32_t ic_type; /* 0x004 */ 69 uint32_t dist_ident; /* 0x008 */ 70 uint32_t res1[29]; /* [0x00C, 0x080) */ 72 uint32_t security[32]; /* [0x080, 0x100) */ 74 uint32_t enable_set[32]; /* [0x100, 0x180) */ 75 uint32_t enable_clr[32]; /* [0x180, 0x200) */ 76 uint32_t pending_set[32]; /* [0x200, 0x280) */ 77 uint32_t pending_clr[32]; /* [0x280, 0x300) */ 78 uint32_t activ [all...] |
H A D | priv_timer.h | 21 uint32_t load; 22 uint32_t count; 23 uint32_t ctrl; 24 uint32_t ints;
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/seL4-l4v-10.1.1/l4v/tools/autocorres/tests/proof-tests/ |
H A D | word_abs_fn_call.c | 12 typedef unsigned int uint32_t; typedef 14 uint8_t foo(int a, uint32_t b, uint8_t c) 19 uint8_t bar(int a, uint32_t b, uint8_t c) 24 uint32_t foo2(int a, uint32_t b, uint8_t c) 29 uint32_t bar2(int a, uint32_t b, uint8_t c) 34 uint8_t foo3(int a, uint32_t b, uint8_t c) 39 uint8_t bar3(int a, uint32_t b, uint8_t c) 44 uint32_t foo [all...] |
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/32/mode/ |
H A D | types.h | 19 typedef uint32_t timestamp_t;
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/seL4-l4v-10.1.1/seL4/include/plat/spike/plat/machine/ |
H A D | fdt.h | 33 uint32_t fdt_size(void *fdt);
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/seL4-l4v-10.1.1/seL4/src/arch/arm/machine/ |
H A D | l2c_310.c | 108 uint32_t cache_id; /* 0x000 */ 109 uint32_t cache_type; /* 0x004 */ 110 uint32_t res[62]; 114 uint32_t control; /* 0x100 */ 115 uint32_t aux_control; /* 0x104 */ 116 uint32_t tag_ram_control; /* 0x108 */ 117 uint32_t data_ram_control; /* 0x10C */ 118 uint32_t res[60]; 122 uint32_t ev_counter_ctrl; /* 0x200 */ 123 uint32_t ev_counter1_cf [all...] |
/seL4-l4v-10.1.1/seL4/include/plat/spike/plat/ |
H A D | machine.h | 40 typedef uint32_t interrupt_t; 41 typedef uint32_t irq_t;
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/seL4-l4v-10.1.1/l4v/tools/c-parser/testfiles/ |
H A D | bug_mvt20110302.c | 11 typedef unsigned long uint32_t; typedef 12 typedef uint32_t vptr_t; 15 uint32_t words[2]; 20 uint32_t words[2];
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/seL4-l4v-10.1.1/seL4/include/arch/arm/armv/armv6/armv/ |
H A D | benchmark_irqHandler.h | 18 uint32_t pmcr;
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