Searched refs:PAGE_BITS (Results 1 - 25 of 38) sorted by relevance

12

/seL4-l4v-10.1.1/seL4/include/plat/exynos4/plat/machine/
H A Dhardware.h63 { /* .start */ CHIPID_PADDR , /* .end */ CHIPID_PADDR + (1 << PAGE_BITS) },
64 { /* .start */ SYSREG_PADDR , /* .end */ SYSREG_PADDR + (1 << PAGE_BITS) },
65 { /* .start */ PMU_PADDR , /* .end */ PMU_PADDR + (5 << PAGE_BITS) },
66 { /* .start */ CMU_TOP_PART_PADDR , /* .end */ CMU_TOP_PART_PADDR + (13 << PAGE_BITS) },
67 { /* .start */ SMDMA0_PADDR , /* .end */ SMDMA0_PADDR + (1 << PAGE_BITS) },
68 { /* .start */ CMU_DMC_PART_PADDR , /* .end */ CMU_DMC_PART_PADDR + (9 << PAGE_BITS) },
69 { /* .start */ NSMDMA0_PADDR , /* .end */ NSMDMA0_PADDR + (1 << PAGE_BITS) },
71 // { /* .start */ MCT_PADDR , /* .end */ MCT_PADDR + (1 << PAGE_BITS) },
72 { /* .start */ SSS_PADDR , /* .end */ SSS_PADDR + (1 << PAGE_BITS) },
73 { /* .start */ WDT_PADDR , /* .end */ WDT_PADDR + (1 << PAGE_BITS) },
[all...]
/seL4-l4v-10.1.1/seL4/include/plat/exynos5/plat/machine/
H A Dhardware.h67 { /* ,start */ SECURE_FIRMWARE , /* .end */ SECURE_FIRMWARE + (16 << PAGE_BITS) },
68 { /* .start */ AUDSS_PADDR , /* .end */ AUDSS_PADDR + (1 << PAGE_BITS) },
69 { /* .start */ AUDIO_GPIO_PADDR , /* .end */ AUDIO_GPIO_PADDR + (1 << PAGE_BITS) },
70 { /* .start */ CHIP_ID_PADDR , /* .end */ CHIP_ID_PADDR + (1 << PAGE_BITS) },
71 { /* .start */ CMU_CPU_PADDR , /* .end */ CMU_CPU_PADDR + (1 << PAGE_BITS) },
72 { /* .start */ CMU_CORE_PADDR , /* .end */ CMU_CORE_PADDR + (1 << PAGE_BITS) },
73 { /* .start */ CMU_ACP_PADDR , /* .end */ CMU_ACP_PADDR + (1 << PAGE_BITS) },
74 { /* .start */ CMU_ISP_PADDR , /* .end */ CMU_ISP_PADDR + (1 << PAGE_BITS) },
75 { /* .start */ CMU_TOP_PADDR , /* .end */ CMU_TOP_PADDR + (1 << PAGE_BITS) },
76 { /* .start */ CMU_LEX_PADDR , /* .end */ CMU_LEX_PADDR + (1 << PAGE_BITS) },
[all...]
/seL4-l4v-10.1.1/seL4/include/plat/apq8064/plat/machine/
H A Dhardware.h63 { /* .start */ RPM_PADDR , /* .end */ RPM_PADDR + (1 << PAGE_BITS) },
64 { /* .start */ RPM_TIMERS_PADDR , /* .end */ RPM_TIMERS_PADDR + (1 << PAGE_BITS) },
65 { /* .start */ RPM_MSG_RAM_XPU_PADDR , /* .end */ RPM_MSG_RAM_XPU_PADDR + (1 << PAGE_BITS) },
66 { /* .start */ MPM_PADDR , /* .end */ MPM_PADDR + (1 << PAGE_BITS) },
67 { /* .start */ PA1_SSBI2_CFG_PADDR , /* .end */ PA1_SSBI2_CFG_PADDR + (1 << PAGE_BITS) },
68 { /* .start */ PA1_XPU_PADDR , /* .end */ PA1_XPU_PADDR + (1 << PAGE_BITS) },
69 { /* .start */ PA1_SSBI2_CMD_PADDR , /* .end */ PA1_SSBI2_CMD_PADDR + (1 << PAGE_BITS) },
70 { /* .start */ PA2_SSBI2_CFG_PADDR , /* .end */ PA2_SSBI2_CFG_PADDR + (1 << PAGE_BITS) },
71 { /* .start */ SEC_CTRL_PADDR , /* .end */ SEC_CTRL_PADDR + (1 << PAGE_BITS) },
72 { /* .start */ TLMM_PADDR , /* .end */ TLMM_PADDR + (1 << PAGE_BITS) },
[all...]
/seL4-l4v-10.1.1/seL4/include/plat/omap3/plat/machine/
H A Dhardware.h64 { ETHERNET_BASE_PADDR , ETHERNET_BASE_PADDR + ( 1 << PAGE_BITS) },
68 // { BOOT_ROM0_PADDR , BOOT_ROM0_PADDR + (20 << PAGE_BITS) },
69 // { BOOT_ROM1_PADDR , BOOT_ROM1_PADDR + ( 8 << PAGE_BITS) },
70 // { SRAM_INTERNAL_PADDR , SRAM_INTERNAL_PADDR + (16 << PAGE_BITS) },
74 { SYSTEM_CONTROL_MODULE_PADDR , SYSTEM_CONTROL_MODULE_PADDR + ( 2 << PAGE_BITS) },
75 { CLOCK_MANAGER_PADDR , CLOCK_MANAGER_PADDR + ( 2 << PAGE_BITS) },
76 { L4_CORE_CONFIG_PADDR , L4_CORE_CONFIG_PADDR + ( 2 << PAGE_BITS) },
77 { DISPLAY_SUBSYSTEM_PADDR , DISPLAY_SUBSYSTEM_PADDR + ( 2 << PAGE_BITS) },
78 { SDMA_PADDR , SDMA_PADDR + ( 2 << PAGE_BITS) },
79 { I2C3_PADDR , I2C3_PADDR + ( 2 << PAGE_BITS) },
[all...]
/seL4-l4v-10.1.1/seL4/include/plat/pc99/plat/machine/
H A Ddevices.h18 #define PPTR_IOAPIC_START (PPTR_APIC + BIT(PAGE_BITS))
19 #define PPTR_DRHU_START (PPTR_IOAPIC_START + BIT(PAGE_BITS) * CONFIG_MAX_NUM_IOAPIC)
21 #define MAX_NUM_DRHU ((-PPTR_DRHU_START) >> PAGE_BITS)
/seL4-l4v-10.1.1/seL4/include/plat/hikey/plat/machine/
H A Dhardware.h53 { /* .start = */ UART0_PADDR, /* .end = */ UART0_PADDR + (1 << PAGE_BITS) },
54 { /* .start = */ UART1_PADDR, /* .end = */ UART1_PADDR + (1 << PAGE_BITS) },
55 { /* .start = */ UART2_PADDR, /* .end = */ UART2_PADDR + (1 << PAGE_BITS) },
56 { /* .start = */ UART3_PADDR, /* .end = */ UART3_PADDR + (1 << PAGE_BITS) },
57 { /* .start = */ UART4_PADDR, /* .end = */ UART4_PADDR + (1 << PAGE_BITS) },
58 { /* .start = */ GIC_PADDR, /* .end = */ GIC_PADDR + ((1 << PAGE_BITS) * 8) },
59 { /* .start = */ RTC0_PADDR, /* .end = */ RTC0_PADDR + (1 << PAGE_BITS) },
60 { /* .start = */ RTC1_PADDR, /* .end = */ RTC1_PADDR + (1 << PAGE_BITS) },
61 { /* .start = */ DMTIMER0_PADDR, /* .end = */ DMTIMER0_PADDR + (1 << PAGE_BITS) },
62 { /* .start = */ DMTIMER1_PADDR, /* .end = */ DMTIMER1_PADDR + (1 << PAGE_BITS) },
[all...]
/seL4-l4v-10.1.1/seL4/include/plat/zynqmp/plat/machine/
H A Dhardware.h64 { /* .start = */ UART0_PADDR , /* .end = */ UART0_PADDR + ( 1 << PAGE_BITS)},
65 { /* .start = */ UART1_PADDR , /* .end = */ UART1_PADDR + ( 1 << PAGE_BITS)},
66 { /* .start = */ TTC0_PADDR , /* .end = */ TTC0_PADDR + ( 1 << PAGE_BITS)},
67 { /* .start = */ TTC1_PADDR , /* .end = */ TTC1_PADDR + ( 1 << PAGE_BITS)},
68 { /* .start = */ TTC2_PADDR , /* .end = */ TTC2_PADDR + ( 1 << PAGE_BITS)},
69 { /* .start = */ TTC3_PADDR , /* .end = */ TTC3_PADDR + ( 1 << PAGE_BITS)},
71 { /* .start = */ I2C0_PADDR , /* .end = */ I2C0_PADDR + ( 1 << PAGE_BITS)},
72 { /* .start = */ I2C1_PADDR , /* .end = */ I2C1_PADDR + ( 1 << PAGE_BITS)},
73 { /* .start = */ GPIO_PADDR , /* .end = */ GPIO_PADDR + ( 1 << PAGE_BITS)},
/seL4-l4v-10.1.1/l4v/tools/c-parser/testfiles/
H A Dbugzilla180.c14 #define PAGE_BITS 12 macro
17 #define PPTR_DRHU_START (PPTR_APIC + BIT(PAGE_BITS))
18 #define MAX_NUM_DRHU ((-PPTR_DRHU_START) >> PAGE_BITS)
19 #define MAX_NUM_DRHU_VARIANT ((-(int32_t)PPTR_DRHU_START) >> PAGE_BITS)
/seL4-l4v-10.1.1/seL4/include/plat/am335x/plat/machine/
H A Dhardware.h73 { /* .start = */ UART0_PADDR, /* .end = */ UART0_PADDR + (1 << PAGE_BITS) },
74 { /* .start = */ DMTIMER2_PADDR, /* .end = */ DMTIMER2_PADDR + (1 << PAGE_BITS) },
75 { /* .start = */ DMTIMER3_PADDR, /* .end = */ DMTIMER3_PADDR + (1 << PAGE_BITS) },
76 { /* .start = */ DMTIMER4_PADDR, /* .end = */ DMTIMER4_PADDR + (1 << PAGE_BITS) },
77 { /* .start = */ DMTIMER5_PADDR, /* .end = */ DMTIMER5_PADDR + (1 << PAGE_BITS) },
78 { /* .start = */ DMTIMER6_PADDR, /* .end = */ DMTIMER6_PADDR + (1 << PAGE_BITS) },
79 { /* .start = */ DMTIMER7_PADDR, /* .end = */ DMTIMER7_PADDR + (1 << PAGE_BITS) },
80 { /* .start = */ WDT1_PADDR, /* .end = */ WDT1_PADDR + (1 << PAGE_BITS) },
81 { /* .start = */ CMPER_PADDR, /* .end = */ CMPER_PADDR + (1 << PAGE_BITS) },
82 { /* .start = */ CTRL_PADDR, /* .end = */ CTRL_PADDR + (1 << PAGE_BITS) },
[all...]
/seL4-l4v-10.1.1/seL4/include/plat/bcm2837/plat/machine/
H A Dhardware.h59 { /* .start */ SDHC_PADDR , /* .end */ SDHC_PADDR + (1u << PAGE_BITS) },
60 { /* .start */ USB2_PADDR , /* .end */ USB2_PADDR + (1u << PAGE_BITS) },
61 { /* .start */ UART_PADDR , /* .end */ UART_PADDR + (1u << PAGE_BITS) },
62 { /* .start */ TIMER_PADDR , /* .end */ TIMER_PADDR + (1u << PAGE_BITS) },
/seL4-l4v-10.1.1/seL4/include/plat/allwinnerA20/plat/machine/
H A Dhardware.h58 { SPI0_PADDR , SPI0_PADDR + ( 2 << PAGE_BITS) },
59 { SPI1_PADDR , SPI1_PADDR + ( 2 << PAGE_BITS) },
/seL4-l4v-10.1.1/seL4/include/
H A Dbootinfo.h20 #define BI_FRAME_SIZE_BITS PAGE_BITS
/seL4-l4v-10.1.1/seL4/src/arch/arm/api/
H A Dfaults.c46 ipa = (addressTranslateS1CPR(va) & ~MASK(PAGE_BITS)) | (va & MASK(PAGE_BITS));
/seL4-l4v-10.1.1/seL4/src/arch/x86/kernel/
H A Dx2apic.c101 assert(IS_ALIGNED(startup_addr, PAGE_BITS));
104 startup_addr >>= PAGE_BITS; local
H A Dxapic.c108 assert(IS_ALIGNED(startup_addr, PAGE_BITS));
111 startup_addr >>= PAGE_BITS; local
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/64/mode/machine/
H A Dhardware.h19 #define PAGE_BITS seL4_PageBits macro
/seL4-l4v-10.1.1/seL4/include/plat/imx7/plat/machine/
H A Dhardware.h31 ARM_MP_PADDR + BIT(PAGE_BITS),
37 ARM_MP_PADDR + BIT(PAGE_BITS) * 2,
/seL4-l4v-10.1.1/seL4/include/arch/riscv/arch/machine/
H A Dhardware.h34 #define PAGE_BITS seL4_PageBits macro
/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/machine/
H A Dhardware.h20 #define PAGE_BITS seL4_PageBits macro
/seL4-l4v-10.1.1/seL4/src/plat/pc99/machine/
H A Dioapic.c48 *(volatile uint32_t*)((word_t)(PPTR_IOAPIC_START + ioapic * BIT(PAGE_BITS)) + reg) = value;
53 return *(volatile uint32_t*)((word_t)(PPTR_IOAPIC_START + ioapic * BIT(PAGE_BITS)) + reg);
H A Dintel-vtd.c97 return *(volatile uint32_t*)(PPTR_DRHU_START + (drhu_id << PAGE_BITS) + offset);
102 *(volatile uint32_t*)(PPTR_DRHU_START + (drhu_id << PAGE_BITS) + offset) = value;
108 return *(volatile uint64_t *)(PPTR_DRHU_START + (drhu_id << PAGE_BITS) + offset);
113 *(volatile uint64_t *)(PPTR_DRHU_START + (drhu_id << PAGE_BITS) + offset) = value;
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/32/mode/kernel/
H A Dvspace.h20 #define PD_ASID_SLOT (0xff000000 >> (PT_INDEX_BITS + PAGE_BITS))
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/32/mode/machine/
H A Dhardware.h17 #define PAGE_BITS seL4_PageBits macro
/seL4-l4v-10.1.1/seL4/include/plat/zynq7000/plat/machine/
H A Dhardware.h33 MPCORE_PRIV_PADDR + BIT(PAGE_BITS),
/seL4-l4v-10.1.1/seL4/include/plat/imx31/plat/machine/
H A Dhardware.h65 { .start = UART_PADDR, .end = UART_PADDR + BIT(PAGE_BITS) }, /* IMX31 UART 1 */

Completed in 103 milliseconds

12