1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the GNU General Public License version 2. Note that NO WARRANTY is provided. 8 * See "LICENSE_GPLv2.txt" for details. 9 * 10 * @TAG(DATA61_GPL) 11 */ 12 13#ifndef __PLAT_MACHINE_HARDWARE_H 14#define __PLAT_MACHINE_HARDWARE_H 15#include <config.h> 16#include <types.h> 17#include <basic_types.h> 18#include <linker.h> 19#include <plat/machine.h> 20#include <plat/machine/devices.h> 21#include <plat_mode/machine/hardware.h> 22#include <machine/io.h> 23 24#define physBase 0x01000000 25 26static const kernel_frame_t BOOT_RODATA kernel_devices[] = { 27 { 28 /* BCM2837 Interrupt controller */ 29 INTC_PADDR, 30 INTC_PPTR, 31 true /* armExecuteNever */ 32 }, 33 { 34 /* ARM Interrupt controller ? */ 35 ARM_LOCAL_PADDR, 36 ARM_LOCAL_PPTR, 37 true /* armExecuteNever */ 38#ifdef CONFIG_PRINTING 39 }, 40 { 41 /* UART */ 42 UART_PADDR, 43 UART_PPTR, 44 true /* armExecuteNever */ 45#endif /* CONFIG_PRINTING */ 46 } 47}; 48 49 50/* Available physical memory regions on platform (RAM) */ 51/* NOTE: Regions are not allowed to be adjacent! */ 52const p_region_t BOOT_RODATA avail_p_regs[] = { 53 /* RPI has 1 GiB but it is split between the videocard and the processor. 54 Currently the processor gets 128MiB as according to the current uboot */ 55 { .start = 0x01000000, .end = 0x08000000 } 56}; 57 58const p_region_t BOOT_RODATA dev_p_regs[] = { 59 { /* .start */ SDHC_PADDR , /* .end */ SDHC_PADDR + (1u << PAGE_BITS) }, 60 { /* .start */ USB2_PADDR , /* .end */ USB2_PADDR + (1u << PAGE_BITS) }, 61 { /* .start */ UART_PADDR , /* .end */ UART_PADDR + (1u << PAGE_BITS) }, 62 { /* .start */ TIMER_PADDR , /* .end */ TIMER_PADDR + (1u << PAGE_BITS) }, 63}; 64 65void initL2Cache(void); 66 67static inline void plat_cleanL2Range(paddr_t start, paddr_t end) {} 68static inline void plat_invalidateL2Range(paddr_t start, paddr_t end) {} 69static inline void plat_cleanInvalidateL2Range(paddr_t start, paddr_t end) {} 70static inline void plat_cleanInvalidateCache(void) {} 71 72#endif /* !__PLAT_MACHINE_HARDWARE_H */ 73