/seL4-camkes-master/projects/musllibc/arch/mips/ |
H A D | pthread_arch.h | 4 register char *tp __asm__("$3"); 5 __asm__ __volatile__ (".word 0x7c03e83b" : "=r" (tp) ); 7 char *tp; 8 __asm__ __volatile__ ("rdhwr %0, $29" : "=r" (tp) ); 10 return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
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/seL4-camkes-master/projects/musllibc/arch/mips64/ |
H A D | pthread_arch.h | 4 register char *tp __asm__("$3"); 5 __asm__ __volatile__ (".word 0x7c03e83b" : "=r" (tp) ); 7 char *tp; 8 __asm__ __volatile__ ("rdhwr %0, $29" : "=r" (tp) ); 10 return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
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/seL4-camkes-master/projects/musllibc/arch/mipsn32/ |
H A D | pthread_arch.h | 4 register char *tp __asm__("$3"); 5 __asm__ __volatile__ (".word 0x7c03e83b" : "=r" (tp) ); 7 char *tp; 8 __asm__ __volatile__ ("rdhwr %0, $29" : "=r" (tp) ); 10 return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
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/seL4-camkes-master/projects/musllibc/arch/or1k/ |
H A D | pthread_arch.h | 1 /* or1k use variant I, but with the twist that tp points to the end of TCB */ 5 char *tp; local 6 __asm__ __volatile__ ("l.ori %0, r10, 0" : "=r" (tp) ); 8 register char *tp __asm__("r10"); 9 __asm__ __volatile__ ("" : "=r" (tp) ); 11 return (struct pthread *) (tp - sizeof(struct pthread));
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/seL4-camkes-master/projects/musllibc/arch/powerpc/ |
H A D | pthread_arch.h | 4 char *tp; local 5 __asm__ __volatile__ ("mr %0, 2" : "=r"(tp) : : ); 7 register char *tp __asm__("r2"); 8 __asm__ __volatile__ ("" : "=r" (tp) ); 10 return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
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/seL4-camkes-master/projects/musllibc/src/time/ |
H A D | ftime.c | 4 int ftime(struct timeb *tp) argument 8 tp->time = ts.tv_sec; 9 tp->millitm = ts.tv_nsec / 1000000; 10 tp->timezone = tp->dstflag = 0;
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/seL4-camkes-master/projects/sel4runtime/include/sel4_arch/ia32/sel4runtime/ |
H A D | thread_arch.h | 20 sel4runtime_uintptr_t tp; local 21 __asm__ __volatile__("movl %%gs:0,%0" : "=r"(tp)); 22 return tp;
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/seL4-camkes-master/projects/musllibc/arch/riscv/ |
H A D | pthread_arch.h | 4 char *tp; local 5 __asm__ __volatile__ ("or %0, t1, x0" : "=r" (tp) ); 7 register char *tp __asm__("t1"); 9 return (struct pthread *) (tp - sizeof(struct pthread));
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/seL4-camkes-master/projects/musllibc/arch/riscv_sel4/ |
H A D | pthread_arch.h | 4 char *tp; local 5 __asm__ __volatile__ ("or %0, t1, x0" : "=r" (tp) ); 7 register char *tp __asm__("t1"); 9 return (struct pthread *) (tp - sizeof(struct pthread));
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/seL4-camkes-master/projects/musllibc/arch/powerpc64/ |
H A D | pthread_arch.h | 3 register char *tp __asm__("r13"); 4 __asm__ __volatile__ ("" : "=r" (tp) ); 5 return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
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/seL4-camkes-master/kernel/tools/ |
H A D | umm.py | 13 # We assume length tp > 0 18 tp = tps[0] 21 if tp == 'Word': 24 elif tp == 'Ptr': 28 elif tp == 'Unit': 31 elif tp == 'Array': 37 return ('Base', tp), rest 56 fl, tp = f.split(':') 57 return (fl.lstrip(), parse_type(tp.split(' '))) 84 name, tp [all...] |
H A D | bitfield_gen.py | 2830 def is_bit_type(tp): 2831 return umm.is_base(tp) & (umm.base_name(tp) in 2841 for path, tp in paths: 2842 tp = umm.base_name(tp) 2844 if tp in type_map: 2845 raise ValueError("Type %s has multiple parents" % tp) 2847 type_map[tp] = (toptp, path)
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/seL4-camkes-master/tools/riscv-pk/machine/ |
H A D | fp_emulation.h | 44 register long tp asm("tp") = read_csr(frm); \ 47 else tp = GET_RM(insn); \ 48 asm volatile ("":"+r"(tp)); }) 50 # define softfloat_roundingMode ({ register int tp asm("tp"); tp; }) 57 # define GET_FCSR() ({ register int tp asm("tp"); tp [all...] |
H A D | mentry.S | 111 STORE tp, 4*REGBYTES(sp) 147 lw tp, (sp) # Move the emulated FCSR from x0's save slot into tp. 155 sw tp, (sp) # Move the emulated FCSR from tp into x0's save slot. 166 LOAD tp, 4*REGBYTES(sp)
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/seL4-camkes-master/projects/sel4runtime/include/sel4_arch/x86_64/sel4runtime/ |
H A D | thread_arch.h | 63 sel4runtime_uintptr_t tp; local 64 __asm__ __volatile__("mov %%fs:0,%0" : "=r"(tp)); 65 return tp;
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/seL4-camkes-master/kernel/src/arch/riscv/machine/ |
H A D | registerset.c | 31 tp,
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/seL4-camkes-master/kernel/include/arch/riscv/arch/machine/ |
H A D | registerset.h | 24 tp = 3, TP = 3, enumerator in enum:_register 25 TLS_BASE = tp,
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/seL4-camkes-master/kernel/libsel4/arch_include/riscv/sel4/arch/ |
H A D | types.h | 64 seL4_Word tp; member in struct:seL4_UserContext_
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/seL4-camkes-master/projects/seL4_libs/libsel4muslcsys/src/ |
H A D | vsyscall.c | 44 void *tp = va_arg(ap, void *); local 57 asm volatile("wrfsbase %0" :: "r"(tp)); 63 seL4_TCB_SetTLSBase(tcb, (seL4_Word)tp); 68 boot_set_thread_area_arg = tp;
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/seL4-camkes-master/projects/seL4_libs/libsel4debug/arch_include/riscv/sel4debug/arch/ |
H A D | registers.h | 54 "tp", 95 compile_time_assert(sp_correct_position, offsetof(seL4_UserContext, tp) == 31 * sizeof(seL4_Word));
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/seL4-camkes-master/projects/seL4_libs/libsel4utils/src/ |
H A D | thread.c | 176 uintptr_t tp = (uintptr_t)sel4runtime_write_tls_image((void *)tls_base); local 178 sel4runtime_set_tls_variable(tp, __sel4_ipc_buffer, ipc_buffer_addr); 195 error = seL4_TCB_SetTLSBase(thread->tcb.cptr, tp);
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/seL4-camkes-master/kernel/src/arch/riscv/ |
H A D | traps.S | 41 STORE tp, (3*REGBYTES)(t0)
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/seL4-camkes-master/kernel/manual/tools/libsel4_tools/ |
H A D | bitfield_gen.py | 2830 def is_bit_type(tp): 2831 return umm.is_base(tp) & (umm.base_name(tp) in 2841 for path, tp in paths: 2842 tp = umm.base_name(tp) 2844 if tp in type_map: 2845 raise ValueError("Type %s has multiple parents" % tp) 2847 type_map[tp] = (toptp, path)
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/seL4-camkes-master/kernel/libsel4/tools/ |
H A D | bitfield_gen.py | 2830 def is_bit_type(tp): 2831 return umm.is_base(tp) & (umm.base_name(tp) in 2841 for path, tp in paths: 2842 tp = umm.base_name(tp) 2844 if tp in type_map: 2845 raise ValueError("Type %s has multiple parents" % tp) 2847 type_map[tp] = (toptp, path)
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/seL4-camkes-master/projects/lwip/src/netif/ppp/ |
H A D | eap.c | 317 struct tm *tp; local 326 tp = localtime(&reftime); 329 strftime(tbuf, sizeof (tbuf), "%Y%m%d", tp);
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