History log of /seL4-camkes-master/kernel/libsel4/arch_include/riscv/sel4/arch/types.h
Revision Date Author Comments
# 5c1b81d9 03-Sep-2020 Gerwin Klein <gerwin.klein@data61.csiro.au>

libsel4: fix license tags

These files should have been released under BSD-2-Clause in the first
place (as per parent LICENSE.md file).

Closes #245

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>


# 512a0200 19-Mar-2020 Qian Ge <qian.ge@data61.csiro.au>

replacing all ifndef with pargma once

All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.


# 79da0792 01-Mar-2020 Gerwin Klein <gerwin.klein@data61.csiro.au>

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.


# 09d5e245 20-Mar-2019 Curtis Millar <curtis.millar@data61.csiro.au>

Fix RISC-V registers to reflect calling convention


# 4ea62e51 04-Dec-2018 Edward Pierzchalski <ed.pierzchalski@data61.csiro.au>

riscv: add remaining registers to user context.

The registers a7, s2-11, and t3-6 were missing from seL4_UserContext.
We also add these to frameRegisters and gpRegisters, which are used
to implement the TCB invocations for reading and writing these
registers.

Zero-length arrays aren't valid expressions or types in ISO C, so
to keep the c parser happy we need to either remove gpRegisters or
provide some contents for it.

In the past, frameRegisters and gpRegisters distinguished between
those registers preserved across a syscall and those that weren't.
TCB_CopyRegisters allows the caller to choose which set to copy.

Since we preserve all non-return registers, this distinction isn't
relevant anymore and there's no easy way to justify the members of
frameRegisters and gpRegisters.

We arbitrarily choose to put the 'last' register t6 in gpRegisters,
for consistency with the register list in registerset.h and with the
order that registers are restored.


# 90d3a694 03-Apr-2018 Anna Lyons <Anna.Lyons@data61.csiro.au>

riscv: s/x3/gp and s/x4/tp in seL4_UserContext

This makes seL4_UserContext consistent with frameRegisters


# a8b2e0f9 02-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: seL4_RISCV_VMAttributes matches vm_attributes_t

Updates the user visible seL4_RISCV_VMAttributes definitions to match what is declared
in vm_attributes_t, which is just the executeNever attribute.


# aafa5942 27-Mar-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

RISCV: Place TODOs in the source


# 83ba0847 20-Feb-2018 Hesham Almatary <hesham.almatary@unsw.edu.au>

[SELFOUR-1156] RISC-V Port

Experimental release that supports both RV32 and RV64