Searched refs:VCLK_DIVISOR_VGA0 (Results 1 - 2 of 2) sorted by relevance

/opensolaris-onvv-gate/usr/src/uts/intel/io/drm/
H A Di915_drv.c538 s3_priv->saveVCLK_DIVISOR_VGA0 = S3_READ(VCLK_DIVISOR_VGA0);
663 S3_WRITE(VCLK_DIVISOR_VGA0, s3_priv->saveVCLK_DIVISOR_VGA0);
H A Di915_drv.h1196 #define VCLK_DIVISOR_VGA0 0x6000 macro

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