Searched refs:OUT_RING (Results 1 - 7 of 7) sorted by relevance
| /opensolaris-onvv-gate/usr/src/uts/intel/io/drm/ |
| H A D | radeon_state.c | 452 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
453 OUT_RING((box->y1 << 16) | box->x1);
454 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
455 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
481 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
482 OUT_RING(ctx->pp_misc);
483 OUT_RING(ctx->pp_fog_color);
484 OUT_RING(ctx->re_solid_color);
485 OUT_RING(ctx->rb3d_blendcntl);
486 OUT_RING(ct
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| H A D | r300_cmdbuf.c | 80 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
102 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
104 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
116 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
117 OUT_RING(0);
118 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
297 OUT_RING(CP_PACKET0(reg, sz - 1));
347 OUT_RING(CP_PACKET0(reg, sz - 1));
385 OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
409 OUT_RING(CP_PACKET
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| H A D | i915_dma.c | 394 OUT_RING(cmd);
402 OUT_RING(cmd);
407 OUT_RING(0);
435 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
436 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
437 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
438 OUT_RING(DR4);
442 OUT_RING(GFX_OP_DRAWRECT_INFO);
443 OUT_RING(DR1);
444 OUT_RING((bo
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| H A D | radeon_drv.h | 1045 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1046 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \
1051 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1052 OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \
1057 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1058 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \
1064 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1065 OUT_RING(RADEON_WAIT_CRTC_PFLIP); \
1069 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1070 OUT_RING(RADEON_RB3D_DC_FLUS
1170 #define OUT_RING macro
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| H A D | i915_irq.c | 576 OUT_RING(MI_STORE_DWORD_INDEX);
577 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
578 OUT_RING(dev_priv->counter);
583 OUT_RING(0);
584 OUT_RING(MI_USER_INTERRUPT);
589 OUT_RING(MI_STORE_DWORD_INDEX);
590 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
591 OUT_RING(dev_priv->counter);
592 OUT_RING(MI_USER_INTERRUPT);
606 OUT_RING(
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| H A D | i915_gem.c | 613 OUT_RING(MI_STORE_DWORD_INDEX);
614 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
615 OUT_RING(seqno);
616 OUT_RING(0);
620 OUT_RING(0);
621 OUT_RING(MI_USER_INTERRUPT);
678 OUT_RING(cmd);
679 OUT_RING(0); /* noop */
1005 OUT_RING(cmd);
1006 OUT_RING(
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| H A D | i915_drv.h | 629 #define OUT_RING(n) do { \ macro
630 DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
637 #define OUT_RING(n) do { \ macro
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