Searched refs:IMR (Results 1 - 6 of 6) sorted by relevance

/opensolaris-onvv-gate/usr/src/uts/intel/io/drm/
H A Di915_irq.c49 * we leave them always unmasked in IMR and then control enabling them through
122 I915_WRITE(IMR, dev_priv->irq_mask_reg);
123 (void) I915_READ(IMR);
132 I915_WRITE(IMR, dev_priv->irq_mask_reg);
133 (void) I915_READ(IMR);
968 I915_WRITE(IMR, 0xffffffff);
1018 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1044 I915_WRITE(IMR, 0xffffffff);
H A Di915_drv.c754 s3_priv->saveIMR = S3_READ(IMR);
H A Di915_drv.h245 /** Cached value of IMR to avoid reads in updating the bitfield */
741 #define IMR 0x020a8 macro
/opensolaris-onvv-gate/usr/src/grub/grub-0.97/netboot/
H A Dns83820.c273 #define IMR 0x14 macro
549 // writel(ns->IMR_cache, ns->base + IMR);
772 writel(0, ns->base + IMR);
783 writel(ns->IMR_cache, ns->base + IMR);
786 readl(ns->base + IMR);
845 writel(0, ns->base + IMR);
/opensolaris-onvv-gate/usr/src/uts/common/io/sfe/
H A Dsfereg.h126 #define IMR 0x14 /* Interrupt mask register */ macro
H A Dsfe.c537 OUTL(dp, IMR, 0);
591 OUTL(dp, IMR, 0);
632 OUTL(dp, IMR, 0);
903 OUTL(dp, IMR, lp->our_intr_bits);
929 OUTL(dp, IMR, 0);
971 OUTL(dp, IMR, 0);

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