/openjdk10/hotspot/src/cpu/arm/vm/ |
H A D | c1_LIRAssembler_arm.hpp | 48 void long_compare_helper(LIR_Opr opr1, LIR_Opr opr2);
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H A D | c1_LIRAssembler_arm.cpp | 1816 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { argument 1819 if (opr1 != opr2) { 1837 if (opr1->is_register()) { 1838 reg2reg(opr1, result); 1839 } else if (opr1->is_stack()) { 1840 stack2reg(opr1, result, result->type()); 1841 } else if (opr1->is_constant()) { 1842 const2reg(opr1, result, lir_patch_none, NULL); 1864 if (opr1 == result) { 1866 } else if (opr1 2309 long_compare_helper(LIR_Opr opr1, LIR_Opr opr2) argument 2332 comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) argument [all...] |
/openjdk10/hotspot/src/cpu/aarch64/vm/ |
H A D | c1_LIRAssembler_aarch64.cpp | 1623 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { argument 1641 if (opr1->is_constant() && opr2->is_constant() 1642 && opr1->type() == T_INT && opr2->type() == T_INT) { 1643 jint val1 = opr1->as_jint(); 1654 if (opr1->is_constant() && opr2->is_constant() 1655 && opr1->type() == T_LONG && opr2->type() == T_LONG) { 1656 jlong val1 = opr1->as_jlong(); 1667 if (opr1->is_stack()) { 1668 stack2reg(opr1, FrameMap::rscratch1_opr, result->type()); 1669 opr1 1898 comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) argument [all...] |
/openjdk10/hotspot/src/cpu/ppc/vm/ |
H A D | c1_LIRAssembler_ppc.cpp | 1415 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { argument 1417 if (opr1->is_single_fpu()) { 1418 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg()); 1419 } else if (opr1->is_double_fpu()) { 1420 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg()); 1421 } else if (opr1->is_single_cpu()) { 1429 __ cmplwi(BOOL_RESULT, opr1->as_register(), con); 1432 __ cmplw(BOOL_RESULT, opr1->as_register(), R0); 1436 __ cmpwi(BOOL_RESULT, opr1->as_register(), con); 1439 __ cmpw(BOOL_RESULT, opr1 1560 cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) argument [all...] |
/openjdk10/hotspot/src/cpu/sparc/vm/ |
H A D | c1_LIRAssembler_sparc.cpp | 1460 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { argument 1461 if (opr1->is_single_fpu()) { 1462 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); 1463 } else if (opr1->is_double_fpu()) { 1464 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); 1465 } else if (opr1->is_single_cpu()) { 1471 __ cmp(opr1->as_register(), con); 1474 __ cmp(opr1->as_register(), O7); 1483 __ cmp(opr1->as_register(), 0); 1486 __ cmp(opr1 1550 cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) argument [all...] |
/openjdk10/hotspot/src/cpu/s390/vm/ |
H A D | c1_LIRAssembler_s390.cpp | 328 const FloatRegister opr1 = op->in_opr1()->as_double_reg(), local 332 __ z_madbr(opr3, opr1, opr2); 336 const FloatRegister opr1 = op->in_opr1()->as_float_reg(), local 340 __ z_maebr(opr3, opr1, opr2); 1200 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { argument 1202 if (opr1->is_single_cpu()) { 1203 Register reg1 = opr1->as_register(); 1206 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 1218 if (opr1 1366 cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) argument [all...] |
/openjdk10/hotspot/src/cpu/x86/vm/ |
H A D | c1_LIRAssembler_x86.cpp | 1935 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { argument 1950 if (opr1->is_cpu_register()) { 1951 reg2reg(opr1, result); 1952 } else if (opr1->is_stack()) { 1953 stack2reg(opr1, result, result->type()); 1954 } else if (opr1->is_constant()) { 1955 const2reg(opr1, result, lir_patch_none, NULL); 2568 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { argument 2569 if (opr1->is_single_cpu()) { 2570 Register reg1 = opr1 [all...] |
H A D | macroAssembler_x86.hpp | 467 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 468 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
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H A D | macroAssembler_x86.cpp | 2701 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { argument 2702 ucomisd(opr1, opr2); 2723 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { argument 2724 ucomiss(opr1, opr2);
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/openjdk10/hotspot/src/share/vm/c1/ |
H A D | c1_LIR.hpp | 1611 LIR_Op2(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, CodeEmitInfo* info = NULL) argument 1613 , _opr1(opr1) 1626 LIR_Op2(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) argument 1628 , _opr1(opr1) 1642 LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result = LIR_OprFact::illegalOpr, argument 1645 , _opr1(opr1) 1658 LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, LIR_Opr tmp1, LIR_Opr tmp2 = LIR_OprFact::illegalOpr, argument 1661 , _opr1(opr1) 1749 LIR_Op3(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr opr3, LIR_Opr result, CodeEmitInfo* info = NULL) argument 1751 , _opr1(opr1) 1833 LIR_OpAssert(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, const char* msg, bool halt) argument 2259 lir_assert(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, const char* msg, bool halt) argument [all...] |