/openjdk10/hotspot/src/os_cpu/solaris_sparc/vm/ |
H A D | solaris_sparc.s | 25 !! -- membar
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/openjdk10/hotspot/src/os_cpu/linux_sparc/vm/ |
H A D | linux_sparc.s | 25 # -- membar
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/openjdk10/hotspot/src/cpu/ppc/vm/ |
H A D | macroAssembler_ppc.inline.hpp | 72 inline void MacroAssembler::membar(int bits) { function in class:MacroAssembler 79 inline void MacroAssembler::release() { membar(LoadStore | StoreStore); } 80 inline void MacroAssembler::acquire() { membar(LoadLoad | LoadStore); } 81 inline void MacroAssembler::fence() { membar(LoadLoad | LoadStore | StoreLoad | StoreStore); }
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H A D | c1_LIRGenerator_ppc.cpp | 734 __ membar(); // To be safe. Unsafe semantics are unclear. 1337 __ membar(); 1365 __ membar();
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H A D | c1_LIRAssembler_ppc.cpp | 2910 void LIR_Assembler::membar() { function in class:LIR_Assembler 2923 __ membar(Assembler::LoadLoad); 2927 __ membar(Assembler::StoreStore); 2931 __ membar(Assembler::LoadStore); 2935 __ membar(Assembler::StoreLoad);
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/openjdk10/hotspot/src/cpu/aarch64/vm/ |
H A D | c1_MacroAssembler_aarch64.cpp | 279 membar(StoreStore); 313 membar(StoreStore);
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H A D | templateTable_aarch64.cpp | 1684 __ membar(MacroAssembler::LoadLoad); 1968 __ membar(MacroAssembler::LoadLoad); 2202 __ membar(MacroAssembler::StoreStore); 2406 // membar it's possible for a simple Dekker test to fail if loads 2412 __ membar(MacroAssembler::AnyAny); 2549 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore); 2646 __ membar(MacroAssembler::StoreStore); 2812 __ membar(MacroAssembler::StoreLoad); 2907 __ membar(MacroAssembler::StoreStore); 2954 __ membar(MacroAssemble [all...] |
H A D | c1_LIRAssembler_aarch64.cpp | 1586 __ membar(__ AnyAny); 1592 __ membar(__ AnyAny); 2958 void LIR_Assembler::membar() { function in class:LIR_Assembler 2959 COMMENT("membar"); 2960 __ membar(MacroAssembler::AnyAny); 2964 __ membar(Assembler::LoadLoad|Assembler::LoadStore); 2968 __ membar(Assembler::LoadStore|Assembler::StoreStore); 2972 __ membar(Assembler::LoadLoad); 2976 __ membar(MacroAssembler::StoreStore); 2979 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssemble [all...] |
H A D | macroAssembler_aarch64.cpp | 1752 void MacroAssembler::membar(Membar_mask_bits order_constraint) { 1759 BLOCK_COMMENT("merged membar"); 2125 membar(AnyAny); 2144 membar(AnyAny); 2168 membar(AnyAny); 2187 membar(AnyAny); 3260 membar(StoreLoad); 3267 membar(StoreStore); 3785 membar(Assembler::StoreLoad);
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/openjdk10/hotspot/src/share/vm/c1/ |
H A D | c1_LIRAssembler.hpp | 247 void membar();
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H A D | c1_LIRGenerator.cpp | 1801 __ membar(); 1864 __ membar(); 2283 __ membar(); 2452 if (!support_IRIW_for_not_multiple_copy_atomic_cpu && x->is_volatile() && os::is_MP()) __ membar(); 3236 if (os::is_MP()) __ membar(); 3763 case lir_membar : __ membar(); break;
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H A D | c1_LIRAssembler.cpp | 650 membar();
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/openjdk10/hotspot/src/share/vm/opto/ |
H A D | macro.cpp | 1859 // who thinks he sees a real use of the address by the membar.) 2219 // Note: The membar's associated with the lock/unlock are currently not 2266 MemBarNode* membar = fallthroughproj->unique_ctrl_out()->as_MemBar(); local 2267 assert(membar != NULL && membar->Opcode() == Op_MemBarAcquireLock, ""); 2268 Node* ctrlproj = membar->proj_out(TypeFunc::Control); 2269 Node* memproj = membar->proj_out(TypeFunc::Memory); 2285 MemBarNode* membar = ctrl->in(0)->as_MemBar(); local 2286 assert(membar->Opcode() == Op_MemBarReleaseLock && 2287 mem->is_Proj() && membar [all...] |
H A D | graphKit.cpp | 3164 // The membar serves as a pinch point between both control and all memory slices. 3169 Node* membar = _gvn.transform(mb); local 3170 set_control(_gvn.transform(new ProjNode(membar, TypeFunc::Control))); 3171 set_all_memory_call(membar); 3172 return membar; 3177 // The membar serves as a pinch point between both control and memory(alias_idx). 3183 // The first membar is on the same memory slice as the field store opcode. 3184 // This forces the membar to follow the store. (Bug 6500685 broke this.) 3187 // on the first membar. This prevents later volatile loads or stores 3198 Node* membar local [all...] |
H A D | matcher.cpp | 2454 const MemBarNode* membar = vmb->as_MemBar(); 2458 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) { 2459 Node* p = membar->fast_out(i); 2510 // We must retain this membar if there is an upcoming volatile 2511 // load, which will be followed by acquire membar.
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/openjdk10/hotspot/src/cpu/arm/vm/ |
H A D | c1_LIRAssembler_arm.cpp | 1778 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp); 1811 // FIXME: is full membar really needed instead of just membar_acquire? 1812 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp); 3376 void LIR_Assembler::membar() { function in class:LIR_Assembler 3377 __ membar(MacroAssembler::StoreLoad, Rtemp); 3381 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadLoad | MacroAssembler::LoadStore), Rtemp); 3385 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp); 3389 __ membar(MacroAssembler::LoadLoad, Rtemp); 3393 __ membar(MacroAssembler::StoreStore, Rtemp); 3397 __ membar(MacroAssemble [all...] |
H A D | c1_MacroAssembler_arm.cpp | 199 membar(MacroAssembler::StoreStore, tmp1);
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H A D | macroAssembler_arm.cpp | 1746 void MacroAssembler::membar(Membar_mask_bits order_constraint, Register tmp) { 1765 void MacroAssembler::membar(Membar_mask_bits order_constraint, 1843 membar(MacroAssembler::StoreStore, noreg); 1859 membar(Membar_mask_bits(LoadLoad | LoadStore | StoreStore | StoreLoad), noreg); 1898 membar(Membar_mask_bits(LoadLoad | LoadStore | StoreStore | StoreLoad), tmp); 1918 membar(StoreLoad, noreg); 2390 membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad), tmp2);
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H A D | c1_Runtime1_arm.cpp | 673 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad), tmp1); 857 __ membar(MacroAssembler::StoreStore, tmp1);
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H A D | stubGenerator_arm.cpp | 533 // <fence>; <op>; <membar StoreLoad|StoreStore> 536 // <membar storeload|loadload> ; load-linked; <op>; store-conditional; <membar storeload|storestore> 578 __ membar(MEMBAR_ATOMIC_OP_PRE, prev); 586 __ membar(MEMBAR_ATOMIC_OP_POST, prev); 628 __ membar(MEMBAR_ATOMIC_OP_PRE, prev); 635 __ membar(MEMBAR_ATOMIC_OP_POST, prev); 675 __ membar(MEMBAR_ATOMIC_OP_PRE, temp1); 680 __ membar(MEMBAR_ATOMIC_OP_POST, temp1); 718 __ membar(MEMBAR_ATOMIC_OP_PR [all...] |
H A D | interp_masm_arm.cpp | 452 membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad), noreg); 464 membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore), noreg);
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H A D | templateInterpreterGenerator_arm.cpp | 1168 __ membar(MacroAssembler::StoreStore, Rtemp); 1189 __ membar(MacroAssembler::StoreLoad, Rtemp);
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H A D | macroAssembler_arm.hpp | 479 void membar(Membar_mask_bits order_constraint, Register tmp = noreg); 481 void membar(Membar_mask_bits mask,
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/openjdk10/hotspot/src/cpu/sparc/vm/ |
H A D | macroAssembler_sparc.inline.hpp | 614 // returns if membar generates anything, obviously this code should mirror 615 // membar below. 624 inline void MacroAssembler::membar( Membar_mask_bits const7a ) { function in class:MacroAssembler 636 Assembler::membar(effective_mask);
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/openjdk10/hotspot/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.amd64/src/org/graalvm/compiler/lir/amd64/ |
H A D | AMD64Move.java | 357 masm.membar(barriers);
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