Searched refs:regMPC_CRC_SEL_CONTROL (Results 1 - 6 of 6) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4897 #define regMPC_CRC_SEL_CONTROL 0x039b macro
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H A Ddcn_3_2_1_offset.h4896 #define regMPC_CRC_SEL_CONTROL 0x039b macro
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H A Ddcn_3_1_6_offset.h6807 #define regMPC_CRC_SEL_CONTROL 0x0503 macro
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H A Ddcn_3_1_4_offset.h14072 #define regMPC_CRC_SEL_CONTROL macro
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H A Ddcn_3_1_5_offset.h6346 #define regMPC_CRC_SEL_CONTROL 0x0503 macro
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H A Ddcn_3_1_2_offset.h6587 #define regMPC_CRC_SEL_CONTROL 0x0503 macro
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