Searched refs:regDSCL0_DSCL_UPDATE (Results 1 - 6 of 6) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h3325 #define regDSCL0_DSCL_UPDATE 0x0d0b macro
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H A Ddcn_3_2_1_offset.h3324 #define regDSCL0_DSCL_UPDATE 0x0d0b macro
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H A Ddcn_3_1_6_offset.h4019 #define regDSCL0_DSCL_UPDATE 0x0d0b macro
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H A Ddcn_3_1_4_offset.h4712 #define regDSCL0_DSCL_UPDATE 0x0d0b macro
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H A Ddcn_3_1_5_offset.h3558 #define regDSCL0_DSCL_UPDATE 0x0d0b macro
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H A Ddcn_3_1_2_offset.h3799 #define regDSCL0_DSCL_UPDATE 0x0d0b macro
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