Searched refs:regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX (Results 1 - 4 of 4) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_6_offset.h4278 #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 macro
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H A Ddcn_3_1_4_offset.h4971 #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 macro
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H A Ddcn_3_1_5_offset.h3817 #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 macro
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H A Ddcn_3_1_2_offset.h4058 #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 macro
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