Searched refs:ref_div (Results 1 - 25 of 27) sorted by relevance

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/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_pll.c79 * @ref_div: resulting reference divider
87 unsigned int *fb_div, unsigned int *ref_div)
97 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
98 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
102 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
120 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
136 unsigned ref_div_min, ref_div_max, ref_div; local
211 ref_div_max, &fb_div, &ref_div);
213 (ref_div * post_di
84 amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int nom, unsigned int den, unsigned int post_div, unsigned int fb_div_max, unsigned int ref_div_max, unsigned int *fb_div, unsigned int *ref_div) argument
[all...]
H A Datombios_crtc.h48 u32 ref_div,
H A Damdgpu_atombios_crtc.c336 /* use recommended ref_div for ss */
581 u32 ref_div,
608 args.v1.usRefDiv = cpu_to_le16(ref_div);
618 args.v2.usRefDiv = cpu_to_le16(ref_div);
628 args.v3.usRefDiv = cpu_to_le16(ref_div);
645 args.v5.ucRefDiv = ref_div;
675 args.v6.ucRefDiv = ref_div;
825 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local
854 &fb_div, &frac_fb_div, &ref_div, &post_div);
861 ref_div, fb_di
575 amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct amdgpu_atom_ss *ss) argument
[all...]
H A Damdgpu_atombios.h43 u32 ref_div; member in struct:atom_clock_dividers
H A Damdgpu_atombios.c1030 dividers->ref_div = args.v3.ucRefDiv;
1050 dividers->ref_div = args.v5.ucRefDiv;
1074 dividers->ref_div = args.v6_out.ucPllRefDiv;
/openbsd-current/sys/dev/pci/drm/radeon/
H A Dradeon_display.c925 * @ref_div: resulting reference divider
932 unsigned *fb_div, unsigned *ref_div)
938 *ref_div = min(max(den/post_div, 1u), ref_div_max);
939 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
943 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
960 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
975 unsigned ref_div_min, ref_div_max, ref_div; local
1053 ref_div_max, &fb_div, &ref_div);
1055 (ref_div * post_di
930 avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, unsigned fb_div_max, unsigned ref_div_max, unsigned *fb_div, unsigned *ref_div) argument
1176 uint32_t ref_div; local
[all...]
H A Dradeon_clocks.c47 uint32_t fb_div, ref_div, post_div, sclk; local
54 ref_div =
57 if (ref_div == 0)
60 sclk = fb_div / ref_div;
77 uint32_t fb_div, ref_div, post_div, mclk; local
84 ref_div =
87 if (ref_div == 0)
90 mclk = fb_div / ref_div;
440 int ref_div = spll->reference_div; local
442 if (!ref_div)
[all...]
H A Drv740_dpm.c140 reference_divider = 1 + dividers.ref_div;
147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
215 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
232 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
251 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
H A Drs780_dpm.c87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
453 if ((min_dividers.ref_div != max_dividers.ref_div) ||
455 (max_dividers.ref_div != current_max_dividers.ref_div) ||
988 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; local
992 (post_div * ref_div);
1010 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; local
1014 (post_div * ref_div);
H A Drv730_dpm.c59 reference_divider = 1 + dividers.ref_div;
77 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
137 reference_divider = dividers.ref_div + 1;
152 mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);
H A Datombios_crtc.c619 /* use recommended ref_div for ss */
821 u32 ref_div,
848 args.v1.usRefDiv = cpu_to_le16(ref_div);
858 args.v2.usRefDiv = cpu_to_le16(ref_div);
868 args.v3.usRefDiv = cpu_to_le16(ref_div);
885 args.v5.ucRefDiv = ref_div;
914 args.v6.ucRefDiv = ref_div;
1062 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local
1094 &fb_div, &frac_fb_div, &ref_div, &post_div);
1097 &fb_div, &frac_fb_div, &ref_div,
815 atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct radeon_atom_ss *ss) argument
[all...]
H A Drv770_dpm.c335 reference_divider = dividers->ref_div;
416 if ((dividers.ref_div < 1) || (dividers.ref_div > 5))
434 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
462 mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
512 reference_divider = 1 + dividers.ref_div;
528 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
812 (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) |
2378 pi->ref_div = dividers.ref_div
[all...]
H A Drv770_dpm.h115 u32 ref_div; member in struct:rv7xx_power_info
H A Drv6xx_dpm.c530 (dividers->ref_div + 1);
567 (ref_clk / (dividers.ref_div + 1)),
573 (ref_clk / (dividers.ref_div + 1)));
606 rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);
685 (ref_clk / (dividers.ref_div + 1)),
691 (ref_clk / (dividers.ref_div + 1)));
1960 pi->spll_ref_div = dividers.ref_div + 1;
1967 pi->mpll_ref_div = dividers.ref_div + 1;
H A Dradeon_legacy_crtc.c266 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, argument
271 if (!ref_div)
274 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
H A Dcypress_dpm.c518 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
535 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
559 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
2061 pi->ref_div = dividers.ref_div + 1;
2063 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
H A Dni_dpm.c2022 reference_divider = 1 + dividers.ref_div;
2030 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
2202 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
2219 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
2243 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
4111 pi->ref_div = dividers.ref_div + 1;
4113 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
H A Dradeon_mode.h557 u32 ref_div; member in struct:atom_clock_dividers
H A Dr600.c205 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; local
228 ref_div = 34;
230 ref_div = 4;
233 ref_div + 1, 0xFFF, 2, 30, ~0,
258 UPLL_REF_DIV(ref_div),
H A Dradeon_atombios.c2884 dividers->ref_div = args.v2.ucAction;
2904 dividers->ref_div = args.v3.ucRefDiv;
2924 dividers->ref_div = args.v5.ucRefDiv;
2949 dividers->ref_div = args.v6_out.ucPllRefDiv;
H A Dbtc_dpm.c2608 pi->ref_div = dividers.ref_div + 1;
2610 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
H A Dsi_dpm.c4787 reference_divider = 1 + dividers.ref_div;
4794 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
6966 pi->ref_div = dividers.ref_div + 1;
6968 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.c544 uint32_t ref_div = 0; local
547 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
551 if (ref_div == 2)
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn31/
H A Ddcn31_hubbub.c921 uint32_t ref_div = 0; local
925 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
929 if (ref_div == 2)
/openbsd-current/sys/dev/pci/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.h571 u32 ref_div; member in struct:rv7xx_power_info

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