Searched refs:post_divider (Results 1 - 14 of 14) sorted by relevance
/openbsd-current/sys/dev/pci/drm/radeon/ |
H A D | rv6xx_dpm.h | 34 u32 post_divider; member in struct:rv6xx_sclk_stepping
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H A D | rv730_dpm.c | 50 u32 reference_divider, post_divider; local 62 post_divider = ((dividers.post_div >> 4) & 0xf) + 65 post_divider = 1; 67 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; 90 u32 vco_freq = engine_clock * post_divider; 129 u32 post_divider, reference_divider; local 140 post_divider = ((dividers.post_div >> 4) & 0xf) + 143 post_divider = 1; 165 u32 vco_freq = memory_clock * post_divider;
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H A D | rv6xx_dpm.c | 150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); 152 step->post_divider = 1; 154 step->vco_frequency = clock * step->post_divider; 173 if (step->post_divider == 1) 176 u32 lo_len = (step->post_divider - 2) / 2; 177 u32 hi_len = step->post_divider - 2 - lo_len; 199 next.post_divider = cur->post_divider; 213 return (cur->post_divider > target->post_divider) [all...] |
H A D | radeon_legacy_crtc.c | 742 uint32_t post_divider = 0; local 820 &reference_div, &post_divider); 823 if (post_div->divider == post_divider) 834 post_divider);
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H A D | rv770_dpm.c | 326 u32 post_divider, reference_divider, feedback_divider8; local 334 post_divider = dividers->post_div; 338 (8 * fyclk * reference_divider * post_divider) / reference_clock; 503 u32 reference_divider, post_divider; local 515 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; 517 post_divider = 1; 519 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; 541 u32 vco_freq = engine_clock * post_divider;
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H A D | radeon_mode.h | 563 u32 post_divider; member in struct:atom_clock_dividers
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H A D | ci_dpm.c | 2634 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; 2642 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; 2675 table->VceLevel[count].Divider = (u8)dividers.post_divider; 2708 table->AcpLevel[count].Divider = (u8)dividers.post_divider; 2740 table->SamuLevel[count].Divider = (u8)dividers.post_divider; 2979 table->ACPILevel.SclkDid = (u8)dividers.post_divider; 3171 sclk->SclkDid = (u8)dividers.post_divider;
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H A D | radeon_atombios.c | 2936 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 2953 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
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H A D | cik.c | 9423 tmp |= dividers.post_divider; 9470 tmp |= dividers.post_divider;
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce/ |
H A D | dce_clock_source.c | 120 * @post_divider: Post Divider (already known) 136 uint32_t post_divider, 143 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; 182 * @post_divider: Post Divider (already known) 195 uint32_t post_divider, 208 post_divider, 219 ref_divider * post_divider * 237 pll_settings->pix_clk_post_divider = post_divider; 241 div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); 257 uint32_t post_divider; local 132 calculate_fb_and_fractional_fb_divider( struct calc_pll_clock_source *calc_pll_cs, uint32_t target_pix_clk_100hz, uint32_t ref_divider, uint32_t post_divider, uint32_t *feedback_divider_param, uint32_t *fract_feedback_divider_param) argument 191 calc_fb_divider_checking_tolerance( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings, uint32_t ref_divider, uint32_t post_divider, uint32_t tolerance) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
H A D | amdgpu_atombios.h | 49 u32 post_divider; member in struct:atom_clock_dividers
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H A D | vi.c | 1001 tmp |= dividers.post_divider; 1091 tmp |= dividers.post_divider;
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H A D | amdgpu_atombios.c | 1061 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 1078 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
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H A D | amdgpu_cik.c | 1467 tmp |= dividers.post_divider; 1516 tmp |= dividers.post_divider;
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