Searched refs:optimal_dcfclk_for_uclk (Results 1 - 5 of 5) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c203 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; local
263 &optimal_dcfclk_for_uclk[i], NULL);
264 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz)
265 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
271 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
283 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
287 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
302 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
303 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c199 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; local
257 &optimal_dcfclk_for_uclk[i], NULL);
258 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz)
259 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
265 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
277 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
281 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
282 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
297 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
298 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c701 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; local
747 &optimal_dcfclk_for_uclk[i], NULL);
748 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
749 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
756 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
768 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
772 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
773 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
787 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
788 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c2097 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; local
2153 &optimal_dcfclk_for_uclk[i], NULL);
2155 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2156 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2163 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2175 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2179 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2180 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2194 optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2195 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c2790 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; local
2843 &optimal_dcfclk_for_uclk[i], NULL);
2844 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2845 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2852 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2864 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2868 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2869 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2883 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2884 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[
[all...]

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