dml/dcn321/dcn321_fpu.c

701 		unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
747 					&optimal_dcfclk_for_uclk[i], NULL);
748 			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
749 				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
756 				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
768 			if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
772 				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
773 					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
787 				optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
788 			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];