Searched refs:num_states (Results 1 - 25 of 42) sorted by relevance

12

/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c125 .num_states = 1,
194 unsigned int num_states = 0; local
276 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
278 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
279 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
282 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
283 dram_speed_mts[num_states++] =
291 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
292 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
293 dram_speed_mts[num_states
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c126 .num_states = 1,
198 unsigned int num_states = 0; local
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
285 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
298 dram_speed_mts[num_states
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c212 .num_states = 5,
301 ASSERT(vlevel < dml->soc.num_states);
343 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) {
368 dcn3_01_soc.num_states = clk_table->num_entries;
370 s[dcn3_01_soc.num_states] =
371 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
372 s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c122 .num_states = 1,
696 unsigned int i = 0, j = 0, num_states = 0; local
767 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
769 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
770 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
773 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
774 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
781 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
782 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
783 dram_speed_mts[num_states
[all...]
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_socbb.h78 uint32_t num_states; member in struct:gpu_info_soc_bounding_box_v1_0
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.h61 unsigned int num_states);
H A Ddcn20_fpu.c289 .num_states = 5,
400 .num_states = 5,
511 .num_states = 5,
762 .num_states = 8
1843 unsigned int num_states)
1851 if (num_states == 0)
1867 for (i = 0; i < num_states; i++) {
1898 bb->num_states = num_calculated_states;
1902 bb->clock_limits[num_calculated_states].state = bb->num_states;
1913 for (i = 0; i < bb->num_states;
1839 dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) argument
[all...]
H A Ddisplay_mode_vba_20v2.c1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz,
2671 for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
3548 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3630 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3981 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3983 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],
4000 && i == mode_lib->vba.soc.num_states)
4007 && i == mode_lib->vba.soc.num_states)
4084 if (i != mode_lib->vba.soc.num_states) {
4116 for (i = 0; i <= mode_lib->vba.soc.num_states;
[all...]
H A Ddisplay_mode_vba_20.c1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz,
2598 for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
3441 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3523 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3874 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3889 && i == mode_lib->vba.soc.num_states)
3896 && i == mode_lib->vba.soc.num_states)
3970 if (i != mode_lib->vba.soc.num_states) {
4002 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
4019 for (i = 0; i <= mode_lib->vba.soc.num_states;
[all...]
/openbsd-current/gnu/usr.bin/binutils-2.17/include/
H A Dxtensa-isa-internal.h200 int num_states; member in struct:xtensa_isa_internal_struct
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c150 .num_states = 5,
217 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) {
225 closest_clk_lvl = dcn3_14_soc.num_states - 1;
259 dcn3_14_soc.num_states = clk_table->num_entries;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c133 .num_states = 1,
287 if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
387 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz,
388 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz,
428 else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz)
1177 if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1191 (*vlevel == context->bw_ctx.dml.soc.num_states ||
1210 /* For the case where *vlevel = num_states, bandwidth validation has failed for this config.
1217 if (*vlevel == context->bw_ctx.dml.soc.num_states &&
1241 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states;
2785 unsigned int i = 0, j = 0, num_states = 0; local
[all...]
H A Ddisplay_mode_vba_32.c112 mode_lib->vba.MaxDppclk[v->soc.num_states - 1]));
1654 start_state = v->soc.num_states - 1;
1658 for (i = v->soc.num_states - 1; i >= start_state; i--) {
1705 || i == v->soc.num_states - 1)
1710 || i == v->soc.num_states - 1
1712 && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1
1741 start_state = v->soc.num_states - 1;
2033 for (i = start_state; i < v->soc.num_states; i++) {
2048 mode_lib->vba.MaxDispclk[v->soc.num_states - 1],
2071 mode_lib->vba.MaxDispclk[v->soc.num_states
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c169 .num_states = 5,
413 .num_states = 5,
611 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
643 dcn3_1_soc.num_states = clk_table->num_entries;
704 dcn3_15_soc.num_states = clk_table->num_entries;
750 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) {
760 closest_clk_lvl = dcn3_16_soc.num_states - 1;
795 dcn3_16_soc.num_states = clk_table->num_entries;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c1669 if (vlevel < context->bw_ctx.dml.soc.num_states)
1673 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1686 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1695 if (vlevel == context->bw_ctx.dml.soc.num_states)
1862 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2076 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2092 unsigned int num_states = 0; local
2174 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2176 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2177 dram_speed_mts[num_states
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/
H A Ddm_pp_smu.h229 unsigned int *clock_values_in_khz, unsigned int *num_states);
/openbsd-current/usr.bin/lex/
H A Ddfa.c83 * void check_trailing_context( int nfa_states[num_states+1], int num_states,
97 * nfa_states[1 .. num_states] is the list of NFA states in the DFA.
101 void check_trailing_context (nfa_states, num_states, accset, nacc)
102 int *nfa_states, num_states;
108 for (i = 1; i <= num_states; ++i) {
223 * int *epsclosure( int t[num_states], int *numstates_addr,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1896 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
1901 if (vlevel > context->bw_ctx.dml.soc.num_states)
2050 if (vlevel > context->bw_ctx.dml.soc.num_states)
2123 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2344 unsigned int num_states = 0; local
2351 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
2366 if (clock_limits_available && uclk_states_available && num_states) {
2368 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
2566 if (loaded_bb->num_states == 1) {
2574 } else if (loaded_bb->num_states >
[all...]
/openbsd-current/gnu/usr.bin/binutils-2.17/bfd/
H A Dxtensa-isa.c257 bfd_malloc (isa->num_states * sizeof (xtensa_lookup_entry));
259 for (n = 0; n < isa->num_states; n++)
264 qsort (isa->state_lookup_table, isa->num_states,
462 return intisa->num_states;
1463 if ((ST) < 0 || (ST) >= (INTISA)->num_states) \
1485 if (intisa->num_states != 0)
1488 result = bsearch (&entry, intisa->state_lookup_table, intisa->num_states,
/openbsd-current/usr.bin/systat/
H A Dpftop.c112 size_t num_states = 0; variable
617 if (num_states <= 0)
620 mergesort(state_ord, num_states, sizeof(size_t), ordering->func);
652 num_disp = num_states;
682 num_states = num_states_all;
687 for (n = 0; n < num_states; n++)
692 num_disp = num_states;
/openbsd-current/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c709 unsigned int *clock_values_in_khz, unsigned int *num_states)
717 num_states);
708 pp_nv_get_uclk_dpm_states(struct pp_smu *pp, unsigned int *clock_values_in_khz, unsigned int *num_states) argument
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c1644 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz,
3674 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
3716 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
4070 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
4072 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],
4094 && i == mode_lib->vba.soc.num_states)
4101 && i == mode_lib->vba.soc.num_states)
4178 if (i != mode_lib->vba.soc.num_states) {
4210 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
4227 for (i = 0; i <= mode_lib->vba.soc.num_states;
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h184 * @num_states: It represents the total of Display Power Management
187 unsigned int num_states; member in struct:_vcs_dpi_soc_bounding_box_st
H A Ddisplay_mode_lib.c291 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c138 .num_states = 1,
574 for (i = 0; i < dc->dml.soc.num_states; i++) {
652 for (i = 0; i < dcn3_0_soc.num_states; i++) {

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