Searched refs:mpc_mask (Results 1 - 24 of 24) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c40 mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name
107 const struct dcn201_mpc_mask *mpc_mask,
118 mpc201->mpc_mask = mpc_mask;
103 dcn201_mpc_construct(struct dcn201_mpc *mpc201, struct dc_context *ctx, const struct dcn201_mpc_registers *mpc_regs, const struct dcn201_mpc_shift *mpc_shift, const struct dcn201_mpc_mask *mpc_mask, int num_mpcc) argument
H A Ddcn201_mpc.h76 const struct dcn201_mpc_mask *mpc_mask; member in struct:dcn201_mpc
83 const struct dcn201_mpc_mask *mpc_mask,
H A Ddcn201_resource.c497 static const struct dcn201_mpc_mask mpc_mask = { variable in typeref:struct:dcn201_mpc_mask
733 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c44 mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
165 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A;
167 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
223 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A;
225 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
251 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
253 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
255 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
257 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
259 reg->masks.field_region_end = mpc20->mpc_mask
567 dcn20_mpc_construct(struct dcn20_mpc *mpc20, struct dc_context *ctx, const struct dcn20_mpc_registers *mpc_regs, const struct dcn20_mpc_shift *mpc_shift, const struct dcn20_mpc_mask *mpc_mask, int num_mpcc) argument
[all...]
H A Ddcn20_mpc.h267 const struct dcn20_mpc_mask *mpc_mask; member in struct:dcn20_mpc
274 const struct dcn20_mpc_mask *mpc_mask,
H A Ddcn20_resource.c496 static const struct dcn20_mpc_mask mpc_mask = { variable in typeref:struct:dcn20_mpc_mask
850 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
180 reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;
182 reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B;
185 reg->masks.exp_region0_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
187 reg->masks.exp_region0_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
189 reg->masks.exp_region1_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
191 reg->masks.exp_region1_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
194 reg->masks.field_region_end = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B;
196 reg->masks.field_region_end_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
198 reg->masks.field_region_end_base = mpc30->mpc_mask
1436 dcn30_mpc_construct(struct dcn30_mpc *mpc30, struct dc_context *ctx, const struct dcn30_mpc_registers *mpc_regs, const struct dcn30_mpc_shift *mpc_shift, const struct dcn30_mpc_mask *mpc_mask, int num_mpcc, int num_rmu) argument
[all...]
H A Ddcn30_mpc.h999 const struct dcn30_mpc_mask *mpc_mask; member in struct:dcn30_mpc
1007 const struct dcn30_mpc_mask *mpc_mask,
H A Ddcn30_resource.c553 static const struct dcn30_mpc_mask mpc_mask = { variable in typeref:struct:dcn30_mpc_mask
850 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_mpc.c42 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
53 if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {
60 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
143 reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
145 reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
147 reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
149 reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
152 reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
154 reg->masks.field_region_end_slope = mpc->mpc_mask
1020 dcn32_mpc_construct(struct dcn30_mpc *mpc30, struct dc_context *ctx, const struct dcn30_mpc_registers *mpc_regs, const struct dcn30_mpc_shift *mpc_shift, const struct dcn30_mpc_mask *mpc_mask, int num_mpcc, int num_rmu) argument
[all...]
H A Ddcn32_mpc.h331 const struct dcn30_mpc_mask *mpc_mask,
H A Ddcn32_resource.c463 static const struct dcn30_mpc_mask mpc_mask = { variable in typeref:struct:dcn30_mpc_mask
957 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.h131 const struct dcn_mpc_mask *mpc_mask; member in struct:dcn10_mpc
138 const struct dcn_mpc_mask *mpc_mask,
H A Ddcn10_mpc.c37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
518 const struct dcn_mpc_mask *mpc_mask,
529 mpc10->mpc_mask = mpc_mask;
514 dcn10_mpc_construct(struct dcn10_mpc *mpc10, struct dc_context *ctx, const struct dcn_mpc_registers *mpc_regs, const struct dcn_mpc_shift *mpc_shift, const struct dcn_mpc_mask *mpc_mask, int num_mpcc) argument
H A Ddcn10_resource.c383 static const struct dcn_mpc_mask mpc_mask = { variable in typeref:struct:dcn_mpc_mask
686 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn302/
H A Ddcn302_resource.c642 static const struct dcn30_mpc_mask mpc_mask = { variable in typeref:struct:dcn30_mpc_mask
653 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn303/
H A Ddcn303_resource.c588 static const struct dcn30_mpc_mask mpc_mask = { variable in typeref:struct:dcn30_mpc_mask
599 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c295 static const struct dcn20_mpc_mask mpc_mask = { variable in typeref:struct:dcn20_mpc_mask
1091 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn321/
H A Ddcn321_resource.c463 static const struct dcn30_mpc_mask mpc_mask = { variable in typeref:struct:dcn30_mpc_mask
956 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn315/
H A Ddcn315_resource.c603 static const struct dcn30_mpc_mask mpc_mask = { variable in typeref:struct:dcn30_mpc_mask
1012 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn314/
H A Ddcn314_resource.c610 static const struct dcn30_mpc_mask mpc_mask = { variable in typeref:struct:dcn30_mpc_mask
1086 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn316/
H A Ddcn316_resource.c600 static const struct dcn30_mpc_mask mpc_mask = { variable in typeref:struct:dcn30_mpc_mask
1008 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn301/
H A Ddcn301_resource.c528 static const struct dcn30_mpc_mask mpc_mask = { variable in typeref:struct:dcn30_mpc_mask
804 &mpc_mask,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn31/
H A Ddcn31_resource.c604 static const struct dcn30_mpc_mask mpc_mask = { variable in typeref:struct:dcn30_mpc_mask
1014 &mpc_mask,

Completed in 283 milliseconds