| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 94 #define mmUVD_VCPU_CNTL 0x3D98 macro
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| H A D | uvd_4_2_d.h | 66 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| H A D | uvd_3_1_d.h | 68 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| H A D | uvd_5_0_d.h | 72 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| H A D | uvd_6_0_d.h | 88 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| H A D | uvd_7_0_offset.h | 190 #define mmUVD_VCPU_CNTL 0x0598 macro
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| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | vcn_v3_0.c | 968 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1028 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1037 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1124 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1185 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1202 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1206 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1565 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1570 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
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| H A D | amdgpu_uvd_v4_2.c | 299 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
450 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
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| H A D | uvd_v5_0.c | 375 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
470 WREG32(mmUVD_VCPU_CNTL, 0x0);
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| H A D | amdgpu_uvd_v3_1.c | 341 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
492 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
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| H A D | vcn_v2_5.c | 845 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
907 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
999 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1062 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1082 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1086 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1423 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1428 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
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| H A D | vcn_v2_0.c | 820 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
954 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
1170 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
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| H A D | vcn_v1_0.c | 860 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
993 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
1148 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
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| H A D | uvd_v7_0.c | 901 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
1032 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
1159 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
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| H A D | uvd_v6_0.c | 789 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
901 WREG32(mmUVD_VCPU_CNTL, 0x0);
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 376 #define mmUVD_VCPU_CNTL 0x0598 macro
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| H A D | vcn_2_0_0_offset.h | 658 #define mmUVD_VCPU_CNTL 0x0258 macro
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| H A D | vcn_2_5_offset.h | 729 #define mmUVD_VCPU_CNTL 0x0156 macro
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| H A D | vcn_3_0_0_offset.h | 1105 #define mmUVD_VCPU_CNTL 0x0156 macro
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