Searched refs:mmUVD_UDEC_ADDR_CONFIG (Results 1 - 14 of 14) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h85 #define mmUVD_UDEC_ADDR_CONFIG 0x3BD3 macro
H A Duvd_4_2_d.h34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 macro
H A Duvd_3_1_d.h34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 macro
H A Duvd_5_0_d.h34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 macro
H A Duvd_6_0_d.h34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 macro
H A Duvd_7_0_offset.h60 #define mmUVD_UDEC_ADDR_CONFIG 0x03d3 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h148 #define mmUVD_UDEC_ADDR_CONFIG 0x03d3 macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_uvd_v4_2.c599 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
H A Duvd_v5_0.c303 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
H A Damdgpu_uvd_v3_1.c270 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
H A Dvcn_v1_0.c352 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
428 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
H A Duvd_v6_0.c627 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
H A Duvd_v7_0.c717 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,
H A Dgfx_v6_0.c1707 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);

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