Searched refs:mmUVD_RB_RPTR (Results 1 - 12 of 12) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h47 #define mmUVD_RB_RPTR 0x3c29 macro
H A Duvd_7_0_offset.h100 #define mmUVD_RB_RPTR 0x0429 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h222 #define mmUVD_RB_RPTR 0x0429 macro
H A Dvcn_2_0_0_offset.h934 #define mmUVD_RB_RPTR 0x05e9 macro
H A Dvcn_2_5_offset.h557 #define mmUVD_RB_RPTR 0x00ad macro
H A Dvcn_3_0_0_offset.h887 #define mmUVD_RB_RPTR 0x00ad macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_v2_0.c1084 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1115 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1241 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1554 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
H A Dvcn_v1_0.c951 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1183 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1256 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1599 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
H A Dvcn_v3_0.c1261 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1504 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1640 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1940 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
H A Dvcn_v2_5.c1136 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1362 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1490 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1615 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
H A Duvd_v6_0.c96 return RREG32(mmUVD_RB_RPTR);
863 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
H A Duvd_v7_0.c90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
1114 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

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