Searched refs:mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R (Results 1 - 4 of 4) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h2129 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0eab macro
H A Ddcn_1_0_offset.h4170 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0de5 macro
[all...]
H A Ddcn_2_1_0_offset.h4084 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0eab macro
[all...]
H A Ddcn_2_0_0_offset.h5022 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0eab macro
[all...]

Completed in 695 milliseconds