1/* 2 * Copyright (C) 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 22#ifndef _dcn_2_0_3_OFFSET_HEADER 23#define _dcn_2_0_3_OFFSET_HEADER 24 25 26// addressBlock: dce_dc_dccg_dccg_dispdec 27// base address: 0x0 28#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 29#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 30#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 31#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 32#define mmDP_DTO_DBUF_EN 0x0044 33#define mmDP_DTO_DBUF_EN_BASE_IDX 1 34#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 35#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 36#define mmREFCLK_CNTL 0x0049 37#define mmREFCLK_CNTL_BASE_IDX 1 38#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b 39#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 40#define mmDCCG_PERFMON_CNTL2 0x004e 41#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 42#define mmDCCG_DS_DTO_INCR 0x0053 43#define mmDCCG_DS_DTO_INCR_BASE_IDX 1 44#define mmDCCG_DS_DTO_MODULO 0x0054 45#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 46#define mmDCCG_DS_CNTL 0x0055 47#define mmDCCG_DS_CNTL_BASE_IDX 1 48#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 49#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 50#define mmDPREFCLK_CNTL 0x0058 51#define mmDPREFCLK_CNTL_BASE_IDX 1 52#define mmDCE_VERSION 0x005e 53#define mmDCE_VERSION_BASE_IDX 1 54#define mmDCCG_GTC_CNTL 0x0060 55#define mmDCCG_GTC_CNTL_BASE_IDX 1 56#define mmDCCG_GTC_DTO_INCR 0x0061 57#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 58#define mmDCCG_GTC_DTO_MODULO 0x0062 59#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 60#define mmDCCG_GTC_CURRENT 0x0063 61#define mmDCCG_GTC_CURRENT_BASE_IDX 1 62#define mmDSCCLK0_DTO_PARAM 0x006c 63#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1 64#define mmMILLISECOND_TIME_BASE_DIV 0x0070 65#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 66#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 67#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 68#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 69#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 70#define mmDCCG_PERFMON_CNTL 0x0073 71#define mmDCCG_PERFMON_CNTL_BASE_IDX 1 72#define mmDCCG_GATE_DISABLE_CNTL 0x0074 73#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 74#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 75#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 76#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076 77#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 78#define mmDCCG_CAC_STATUS 0x0077 79#define mmDCCG_CAC_STATUS_BASE_IDX 1 80#define mmMICROSECOND_TIME_BASE_DIV 0x007b 81#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 82#define mmDCCG_GATE_DISABLE_CNTL2 0x007c 83#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 84#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d 85#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 86#define mmDCCG_DISP_CNTL_REG 0x007f 87#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 88#define mmOTG0_PIXEL_RATE_CNTL 0x0080 89#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 90#define mmDP_DTO0_PHASE 0x0081 91#define mmDP_DTO0_PHASE_BASE_IDX 1 92#define mmDP_DTO0_MODULO 0x0082 93#define mmDP_DTO0_MODULO_BASE_IDX 1 94#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 95#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 96#define mmOTG1_PIXEL_RATE_CNTL 0x0084 97#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 98#define mmDP_DTO1_PHASE 0x0085 99#define mmDP_DTO1_PHASE_BASE_IDX 1 100#define mmDP_DTO1_MODULO 0x0086 101#define mmDP_DTO1_MODULO_BASE_IDX 1 102#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 103#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 104#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098 105#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 106#define mmDPPCLK0_DTO_PARAM 0x0099 107#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1 108#define mmDPPCLK1_DTO_PARAM 0x009a 109#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1 110#define mmDPPCLK2_DTO_PARAM 0x009b 111#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1 112#define mmDPPCLK3_DTO_PARAM 0x009c 113#define mmDPPCLK3_DTO_PARAM_BASE_IDX 1 114#define mmDCCG_CAC_STATUS2 0x009f 115#define mmDCCG_CAC_STATUS2_BASE_IDX 1 116#define mmSYMCLKA_CLOCK_ENABLE 0x00a0 117#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 118#define mmSYMCLKB_CLOCK_ENABLE 0x00a1 119#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 120#define mmDCCG_SOFT_RESET 0x00a6 121#define mmDCCG_SOFT_RESET_BASE_IDX 1 122#define mmDSCCLK_DTO_CTRL 0x00a7 123#define mmDSCCLK_DTO_CTRL_BASE_IDX 1 124#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab 125#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 126#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac 127#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 128#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad 129#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 130#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae 131#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 132#define mmDCCG_AUDIO_DTO1_MODULE 0x00af 133#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 134#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 135#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 136#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 137#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 138#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 139#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 140#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 141#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 142#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 143#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 144#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 145#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 146#define mmDPPCLK_DTO_CTRL 0x00b6 147#define mmDPPCLK_DTO_CTRL_BASE_IDX 1 148#define mmDCCG_VSYNC_CNT_CTRL 0x00b8 149#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 150#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9 151#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 152 153 154// addressBlock: dce_dc_dccg_dccg_dfs_dispdec 155// base address: 0x0 156#define mmDENTIST_DISPCLK_CNTL 0x0064 157#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 158 159 160// addressBlock: dce_dc_dmu_rbbmif_dispdec 161// base address: 0x0 162#define mmRBBMIF_TIMEOUT 0x005b 163#define mmRBBMIF_TIMEOUT_BASE_IDX 2 164#define mmRBBMIF_STATUS 0x005c 165#define mmRBBMIF_STATUS_BASE_IDX 2 166#define mmRBBMIF_STATUS_2 0x005d 167#define mmRBBMIF_STATUS_2_BASE_IDX 2 168#define mmRBBMIF_INT_STATUS 0x005e 169#define mmRBBMIF_INT_STATUS_BASE_IDX 2 170#define mmRBBMIF_TIMEOUT_DIS 0x005f 171#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 172#define mmRBBMIF_TIMEOUT_DIS_2 0x0060 173#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 174#define mmRBBMIF_STATUS_FLAG 0x0061 175#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 176 177// addressBlock: dce_dc_hda_az_misc_dispdec 178// base address: 0x0 179#define mmAZ_CLOCK_CNTL 0x0372 180#define mmAZ_CLOCK_CNTL_BASE_IDX 2 181 182 183// addressBlock: dce_dc_hda_azf0endpoint0_dispdec 184// base address: 0x0 185#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 186#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 187#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 188#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 189 190 191// addressBlock: dce_dc_hda_azf0endpoint1_dispdec 192// base address: 0x18 193#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 194#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 195#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 196#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 197 198 199// addressBlock: dce_dc_hda_azf0controller_dispdec 200// base address: 0x0 201#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 202#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 203#define mmAZALIA_AUDIO_DTO 0x03c3 204#define mmAZALIA_AUDIO_DTO_BASE_IDX 2 205#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4 206#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 207#define mmAZALIA_SOCCLK_CONTROL 0x03c5 208#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 209#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 210#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 211#define mmAZALIA_DATA_DMA_CONTROL 0x03c7 212#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 213#define mmAZALIA_BDL_DMA_CONTROL 0x03c8 214#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 215#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9 216#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 217#define mmAZALIA_CORB_DMA_CONTROL 0x03ca 218#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 219#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 220#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 221#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 222#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 223#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3 224#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 225#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 226#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 227#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 228#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 229#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 230#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 231#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9 232#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 233#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da 234#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 235#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db 236#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 237#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc 238#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 239#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd 240#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 241#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de 242#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 243#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df 244#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 245#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0 246#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 247#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1 248#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 249#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2 250#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 251#define mmAZALIA_MEM_PWR_CTRL 0x03ee 252#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 253#define mmAZALIA_MEM_PWR_STATUS 0x03ef 254#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 255 256 257// addressBlock: dce_dc_hda_azf0root_dispdec 258// base address: 0x0 259#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 260#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 261#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 262#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 263#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 264#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 265#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 266#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 267#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 268#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 269#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 270#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 271#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 272#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 273#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 274#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 275#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 276#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 277#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 278#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 279#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 280#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 281#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 282#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 283#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 284#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 285#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 286#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 287 288// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 289// base address: 0x0 290#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 291#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 292#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 293#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 294 295 296// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 297// base address: 0x10 298#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 299#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 300#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 301#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 302 303 304// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec 305// base address: 0x0 306#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf 307#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 308#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0 309#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 310#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1 311#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 312#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2 313#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 314#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3 315#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 316#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4 317#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 318#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5 319#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 320#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6 321#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 322#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7 323#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 324#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8 325#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 326#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9 327#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 328#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da 329#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 330#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db 331#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 332#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc 333#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 334#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd 335#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 336#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de 337#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 338#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df 339#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 340#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef 341#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 342#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0 343#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 344#define mmDCHUBBUB_CRC_CTRL 0x04f1 345#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2 346#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2 347#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 348#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3 349#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 350#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4 351#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 352#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5 353#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 354 355// addressBlock: dce_dc_dchubbub_hubbub_dispdec 356// base address: 0x0 357#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505 358#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 359#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506 360#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 361#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507 362#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 363#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508 364#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 365#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509 366#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 367#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a 368#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2 369#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d 370#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 371#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e 372#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 373#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f 374#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2 375#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512 376#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 377#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513 378#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 379#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514 380#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2 381#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517 382#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 383#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 384#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 385#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519 386#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2 387#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c 388#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 389#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d 390#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 391#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e 392#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 393#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f 394#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 395#define mmVTG0_CONTROL 0x0528 396#define mmVTG0_CONTROL_BASE_IDX 2 397#define mmVTG1_CONTROL 0x0529 398#define mmVTG1_CONTROL_BASE_IDX 2 399#define mmDCHUBBUB_SOFT_RESET 0x052e 400#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2 401#define mmDCHUBBUB_CLOCK_CNTL 0x052f 402#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 403#define mmDCFCLK_CNTL 0x0530 404#define mmDCFCLK_CNTL_BASE_IDX 2 405#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533 406#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 407#define mmDCHUBBUB_CTRL_STATUS 0x0534 408#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2 409#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a 410#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 411#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b 412#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 413#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c 414#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 415#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d 416#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 417#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e 418#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 419#define mmFMON_CTRL 0x0548 420#define mmFMON_CTRL_BASE_IDX 2 421 422 423 424// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 425// base address: 0x0 426#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 427#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 428#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6 429#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 430#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7 431#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 432#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 433#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 434#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 435#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 436#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 437#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 438#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 439#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 440#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 441#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 442#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 443#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 444#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 445#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 446#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 447#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 448#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 449#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 450#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 451#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 452#define mmHUBP0_DCHUBP_CNTL 0x05f3 453#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2 454#define mmHUBP0_HUBP_CLK_CNTL 0x05f4 455#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 456#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6 457#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 458#define mmHUBP0_HUBPREQ_DEBUG 0x05f7 459#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 460#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb 461#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 462#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc 463#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 464 465 466// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 467// base address: 0x0 468#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 469#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 470#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 471#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 472#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 473#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 474#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 475#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 476#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 477#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 478#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 479#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 480#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 481#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 482#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 483#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 484#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 485#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 486#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 487#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 488#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 489#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 490#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 491#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 492#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 493#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 494#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 495#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 496#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 497#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 498#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 499#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 500#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 501#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 502#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 503#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 504#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 505#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 506#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 507#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 508#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 509#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 510#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 511#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 512#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 513#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 514#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 515#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 516#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 517#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 518#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 519#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 520#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 521#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 522#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 523#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 524#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 525#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 526#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 527#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 528#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x062c 529#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 530#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062d 531#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 532#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062e 533#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 534#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062f 535#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 536#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x0630 537#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 538#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x0631 539#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 540#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x0632 541#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 542#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0633 543#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 544#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0634 545#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 546#define mmHUBPREQ0_BLANK_OFFSET_0 0x0646 547#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 548#define mmHUBPREQ0_BLANK_OFFSET_1 0x0647 549#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 550#define mmHUBPREQ0_DST_DIMENSIONS 0x0648 551#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 552#define mmHUBPREQ0_DST_AFTER_SCALER 0x0649 553#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 554#define mmHUBPREQ0_PREFETCH_SETTINGS 0x064a 555#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 556#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x064b 557#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 558#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064c 559#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 560#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064d 561#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 562#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064e 563#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 564#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064f 565#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 566#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x0650 567#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 568#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x0651 569#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 570#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0653 571#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 572#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0658 573#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 574#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0659 575#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 576#define mmHUBPREQ0_NOM_PARAMETERS_6 0x065a 577#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 578#define mmHUBPREQ0_NOM_PARAMETERS_7 0x065b 579#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 580#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065c 581#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 582#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065d 583#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 584#define mmHUBPREQ0_CURSOR_SETTINGS 0x065e 585#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 586#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065f 587#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 588#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x0660 589#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 590#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x0661 591#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 592#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0662 593#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 594 595 596// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 597// base address: 0x0 598#define mmHUBPRET0_HUBPRET_CONTROL 0x066a 599#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 600#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066b 601#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 602#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066c 603#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 604#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066d 605#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 606#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x066e 607#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 608#define mmHUBPRET0_HUBPRET_READ_LINE0 0x066f 609#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 610#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0670 611#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 612#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0671 613#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 614#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0672 615#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 616#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0673 617#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 618 619 620// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 621// base address: 0x0 622#define mmCURSOR0_0_CURSOR_CONTROL 0x0678 623#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 624#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 625#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 626#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 627#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 628#define mmCURSOR0_0_CURSOR_SIZE 0x067b 629#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 630#define mmCURSOR0_0_CURSOR_POSITION 0x067c 631#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 632#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d 633#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 634#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 635#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 636#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f 637#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 638#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 639#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 640#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 641#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 642#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 643#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 644#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 645#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 646#define mmCURSOR0_0_DMDATA_CNTL 0x0684 647#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 648#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685 649#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 650#define mmCURSOR0_0_DMDATA_STATUS 0x0686 651#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 652#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687 653#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 654#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688 655#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 656 657 658 659// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 660// base address: 0x370 661#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 662#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 663#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2 664#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 665#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3 666#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 667#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 668#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 669#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 670#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 671#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 672#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 673#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 674#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 675#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 676#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 677#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 678#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 679#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 680#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 681#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 682#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 683#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 684#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 685#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 686#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 687#define mmHUBP1_DCHUBP_CNTL 0x06cf 688#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2 689#define mmHUBP1_HUBP_CLK_CNTL 0x06d0 690#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 691#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2 692#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 693#define mmHUBP1_HUBPREQ_DEBUG 0x06d3 694#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 695#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 696#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 697#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 698#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 699 700 701// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 702// base address: 0x370 703#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 704#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 705#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 706#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 707#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 708#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 709#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 710#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 711#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 712#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 713#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 714#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 715#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 716#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 717#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 718#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 719#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 720#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 721#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 722#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 723#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 724#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 725#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 726#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 727#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 728#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 729#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 730#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 731#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 732#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 733#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 734#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 735#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 736#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 737#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 738#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 739#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 740#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 741#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 742#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 743#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 744#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 745#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc 746#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 747#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd 748#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 749#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe 750#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 751#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff 752#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 753#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 754#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 755#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 756#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 757#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 758#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 759#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 760#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 761#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 762#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 763#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0708 764#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 765#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0709 766#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 767#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x070a 768#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 769#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x070b 770#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 771#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x070c 772#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 773#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070d 774#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 775#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070e 776#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 777#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070f 778#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 779#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0710 780#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 781#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x0711 782#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 783#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x0712 784#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 785#define mmHUBPREQ1_BLANK_OFFSET_0 0x0722 786#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 787#define mmHUBPREQ1_BLANK_OFFSET_1 0x0723 788#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 789#define mmHUBPREQ1_DST_DIMENSIONS 0x0724 790#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 791#define mmHUBPREQ1_DST_AFTER_SCALER 0x0725 792#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 793#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0726 794#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 795#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0727 796#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 797#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0728 798#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 799#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0729 800#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 801#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x072a 802#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 803#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x072b 804#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 805#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072c 806#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 807#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072d 808#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 809#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072f 810#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 811#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0734 812#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 813#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0735 814#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 815#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0736 816#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 817#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0737 818#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 819#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0738 820#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 821#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0739 822#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 823#define mmHUBPREQ1_CURSOR_SETTINGS 0x073a 824#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 825#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x073b 826#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 827#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073c 828#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 829#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073d 830#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 831#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073e 832#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 833 834 835// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 836// base address: 0x370 837#define mmHUBPRET1_HUBPRET_CONTROL 0x0746 838#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 839#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0747 840#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 841#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x0748 842#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 843#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x0749 844#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 845#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074a 846#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 847#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074b 848#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 849#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074c 850#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 851#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074d 852#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 853#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x074e 854#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 855#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x074f 856#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 857 858 859// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 860// base address: 0x370 861#define mmCURSOR0_1_CURSOR_CONTROL 0x0754 862#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 863#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 864#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 865#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 866#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 867#define mmCURSOR0_1_CURSOR_SIZE 0x0757 868#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 869#define mmCURSOR0_1_CURSOR_POSITION 0x0758 870#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 871#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759 872#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 873#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 874#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 875#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b 876#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 877#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 878#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 879#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 880#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 881#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 882#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 883#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 884#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 885#define mmCURSOR0_1_DMDATA_CNTL 0x0760 886#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 887#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761 888#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 889#define mmCURSOR0_1_DMDATA_STATUS 0x0762 890#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 891#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763 892#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 893#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764 894#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 895 896 897 898// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 899// base address: 0x6e0 900#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d 901#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 902#define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e 903#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 904#define mmHUBP2_DCSURF_TILING_CONFIG 0x079f 905#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 906#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 907#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 908#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 909#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 910#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 911#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 912#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 913#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 914#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 915#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 916#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 917#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 918#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 919#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 920#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 921#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 922#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 923#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 924#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 925#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 926#define mmHUBP2_DCHUBP_CNTL 0x07ab 927#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2 928#define mmHUBP2_HUBP_CLK_CNTL 0x07ac 929#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 930#define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae 931#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 932#define mmHUBP2_HUBPREQ_DEBUG 0x07af 933#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 934#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 935#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 936#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 937#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 938 939 940// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 941// base address: 0x6e0 942#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 943#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 944#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 945#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 946#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 947#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 948#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 949#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 950#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 951#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 952#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 953#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 954#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 955#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 956#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 957#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 958#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 959#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 960#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 961#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 962#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 963#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 964#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 965#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 966#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 967#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 968#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 969#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 970#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 971#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 972#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 973#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 974#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 975#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 976#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 977#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 978#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 979#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 980#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 981#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 982#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 983#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 984#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 985#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 986#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 987#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 988#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da 989#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 990#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db 991#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 992#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc 993#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 994#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd 995#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 996#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de 997#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 998#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df 999#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 1000#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 1001#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 1002#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e4 1003#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 1004#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e5 1005#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 1006#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e6 1007#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 1008#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e7 1009#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 1010#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e8 1011#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 1012#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e9 1013#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 1014#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07ea 1015#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 1016#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07eb 1017#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 1018#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07ec 1019#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 1020#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ed 1021#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 1022#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ee 1023#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 1024#define mmHUBPREQ2_BLANK_OFFSET_0 0x07fe 1025#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 1026#define mmHUBPREQ2_BLANK_OFFSET_1 0x07ff 1027#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 1028#define mmHUBPREQ2_DST_DIMENSIONS 0x0800 1029#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 1030#define mmHUBPREQ2_DST_AFTER_SCALER 0x0801 1031#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 1032#define mmHUBPREQ2_PREFETCH_SETTINGS 0x0802 1033#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 1034#define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0803 1035#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 1036#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0804 1037#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 1038#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0805 1039#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 1040#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0806 1041#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 1042#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0807 1043#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 1044#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0808 1045#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 1046#define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0809 1047#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 1048#define mmHUBPREQ2_FLIP_PARAMETERS_2 0x080b 1049#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 1050#define mmHUBPREQ2_NOM_PARAMETERS_4 0x0810 1051#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 1052#define mmHUBPREQ2_NOM_PARAMETERS_5 0x0811 1053#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 1054#define mmHUBPREQ2_NOM_PARAMETERS_6 0x0812 1055#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 1056#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0813 1057#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 1058#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0814 1059#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 1060#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0815 1061#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 1062#define mmHUBPREQ2_CURSOR_SETTINGS 0x0816 1063#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 1064#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0817 1065#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 1066#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0818 1067#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 1068#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0819 1069#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 1070#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x081a 1071#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 1072 1073 1074// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 1075// base address: 0x6e0 1076#define mmHUBPRET2_HUBPRET_CONTROL 0x0822 1077#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 1078#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0823 1079#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 1080#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0824 1081#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 1082#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0825 1083#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 1084#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0826 1085#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 1086#define mmHUBPRET2_HUBPRET_READ_LINE0 0x0827 1087#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 1088#define mmHUBPRET2_HUBPRET_READ_LINE1 0x0828 1089#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 1090#define mmHUBPRET2_HUBPRET_INTERRUPT 0x0829 1091#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 1092#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082a 1093#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 1094#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082b 1095#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 1096 1097 1098// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec 1099// base address: 0x6e0 1100#define mmCURSOR0_2_CURSOR_CONTROL 0x0830 1101#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 1102#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 1103#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 1104#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 1105#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 1106#define mmCURSOR0_2_CURSOR_SIZE 0x0833 1107#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 1108#define mmCURSOR0_2_CURSOR_POSITION 0x0834 1109#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 1110#define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835 1111#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 1112#define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 1113#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 1114#define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837 1115#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 1116#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 1117#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 1118#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 1119#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 1120#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 1121#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 1122#define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 1123#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 1124#define mmCURSOR0_2_DMDATA_CNTL 0x083c 1125#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 1126#define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d 1127#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 1128#define mmCURSOR0_2_DMDATA_STATUS 0x083e 1129#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 1130#define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f 1131#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 1132#define mmCURSOR0_2_DMDATA_SW_DATA 0x0840 1133#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 1134 1135 1136// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 1137// base address: 0xa50 1138#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879 1139#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 1140#define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a 1141#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 1142#define mmHUBP3_DCSURF_TILING_CONFIG 0x087b 1143#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 1144#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 1145#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 1146#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 1147#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 1148#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 1149#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 1150#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 1151#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 1152#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 1153#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 1154#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 1155#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 1156#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 1157#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 1158#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 1159#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 1160#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 1161#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 1162#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 1163#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 1164#define mmHUBP3_DCHUBP_CNTL 0x0887 1165#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2 1166#define mmHUBP3_HUBP_CLK_CNTL 0x0888 1167#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 1168#define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a 1169#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 1170#define mmHUBP3_HUBPREQ_DEBUG 0x088b 1171#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 1172#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f 1173#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 1174#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 1175#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 1176 1177 1178// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 1179// base address: 0xa50 1180#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 1181#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 1182#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 1183#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 1184#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 1185#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 1186#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 1187#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 1188#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 1189#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 1190#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 1191#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 1192#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 1193#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 1194#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 1195#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 1196#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 1197#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 1198#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 1199#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 1200#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 1201#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 1202#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 1203#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 1204#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 1205#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 1206#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 1207#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 1208#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 1209#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 1210#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 1211#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 1212#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 1213#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 1214#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 1215#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 1216#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 1217#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 1218#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 1219#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 1220#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 1221#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 1222#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 1223#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 1224#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 1225#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 1226#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 1227#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 1228#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 1229#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 1230#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 1231#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 1232#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 1233#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 1234#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba 1235#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 1236#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb 1237#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 1238#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc 1239#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 1240#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08c0 1241#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 1242#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08c1 1243#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 1244#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08c2 1245#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 1246#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c3 1247#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 1248#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c4 1249#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 1250#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c5 1251#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 1252#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c6 1253#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 1254#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c7 1255#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 1256#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c8 1257#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 1258#define mmHUBPREQ3_BLANK_OFFSET_0 0x08da 1259#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 1260#define mmHUBPREQ3_BLANK_OFFSET_1 0x08db 1261#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 1262#define mmHUBPREQ3_DST_DIMENSIONS 0x08dc 1263#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 1264#define mmHUBPREQ3_DST_AFTER_SCALER 0x08dd 1265#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 1266#define mmHUBPREQ3_PREFETCH_SETTINGS 0x08de 1267#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 1268#define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08df 1269#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 1270#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08e0 1271#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 1272#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08e1 1273#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 1274#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e2 1275#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 1276#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e3 1277#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 1278#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e4 1279#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 1280#define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e5 1281#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 1282#define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e7 1283#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 1284#define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ec 1285#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 1286#define mmHUBPREQ3_NOM_PARAMETERS_5 0x08ed 1287#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 1288#define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ee 1289#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 1290#define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ef 1291#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 1292#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08f0 1293#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 1294#define mmHUBPREQ3_PER_LINE_DELIVERY 0x08f1 1295#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 1296#define mmHUBPREQ3_CURSOR_SETTINGS 0x08f2 1297#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 1298#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f3 1299#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 1300#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f4 1301#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 1302#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f5 1303#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 1304#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f6 1305#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 1306 1307 1308// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 1309// base address: 0xa50 1310#define mmHUBPRET3_HUBPRET_CONTROL 0x08fe 1311#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 1312#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x08ff 1313#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 1314#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0900 1315#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 1316#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0901 1317#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 1318#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0902 1319#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 1320#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0903 1321#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 1322#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0904 1323#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 1324#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0905 1325#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 1326#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0906 1327#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 1328#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0907 1329#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 1330 1331 1332// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec 1333// base address: 0xa50 1334#define mmCURSOR0_3_CURSOR_CONTROL 0x090c 1335#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 1336#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 1337#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 1338#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 1339#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 1340#define mmCURSOR0_3_CURSOR_SIZE 0x090f 1341#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 1342#define mmCURSOR0_3_CURSOR_POSITION 0x0910 1343#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 1344#define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911 1345#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 1346#define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 1347#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 1348#define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913 1349#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 1350#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 1351#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 1352#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 1353#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 1354#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 1355#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 1356#define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 1357#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 1358#define mmCURSOR0_3_DMDATA_CNTL 0x0918 1359#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 1360#define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919 1361#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 1362#define mmCURSOR0_3_DMDATA_STATUS 0x091a 1363#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 1364#define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b 1365#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 1366#define mmCURSOR0_3_DMDATA_SW_DATA 0x091c 1367#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 1368 1369// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 1370// base address: 0x0 1371#define mmDPP_TOP0_DPP_CONTROL 0x0cc5 1372#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2 1373#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6 1374#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 1375#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 1376#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 1377#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 1378#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 1379#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9 1380#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 1381#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca 1382#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 1383 1384 1385// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 1386// base address: 0x0 1387#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 1388#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 1389#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0 1390#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 1391#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 1392#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 1393#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 1394#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 1395#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 1396#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 1397#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 1398#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 1399#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 1400#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 1401#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 1402#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 1403#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 1404#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 1405#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 1406#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 1407#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 1408#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 1409#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 1410#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 1411#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 1412#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 1413#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 1414#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 1415 1416 1417// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 1418// base address: 0x0 1419#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0ce0 1420#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 1421#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0ce1 1422#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 1423#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0ce2 1424#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 1425#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0ce3 1426#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 1427 1428 1429// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 1430// base address: 0x0 1431#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cea 1432#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 1433#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0ceb 1434#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 1435#define mmDSCL0_SCL_MODE 0x0cec 1436#define mmDSCL0_SCL_MODE_BASE_IDX 2 1437#define mmDSCL0_SCL_TAP_CONTROL 0x0ced 1438#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 1439#define mmDSCL0_DSCL_CONTROL 0x0cee 1440#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2 1441#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cef 1442#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 1443#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cf0 1444#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 1445#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0cf1 1446#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 1447#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0cf2 1448#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 1449#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0cf3 1450#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 1451#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0cf4 1452#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 1453#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0cf5 1454#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 1455#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0cf6 1456#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 1457#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0cf7 1458#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 1459#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0cf8 1460#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 1461#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0cf9 1462#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 1463#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0cfa 1464#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 1465#define mmDSCL0_SCL_BLACK_OFFSET 0x0cfb 1466#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2 1467#define mmDSCL0_DSCL_UPDATE 0x0cfc 1468#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2 1469#define mmDSCL0_DSCL_AUTOCAL 0x0cfd 1470#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2 1471#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0cfe 1472#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 1473#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0cff 1474#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 1475#define mmDSCL0_OTG_H_BLANK 0x0d00 1476#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2 1477#define mmDSCL0_OTG_V_BLANK 0x0d01 1478#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2 1479#define mmDSCL0_RECOUT_START 0x0d02 1480#define mmDSCL0_RECOUT_START_BASE_IDX 2 1481#define mmDSCL0_RECOUT_SIZE 0x0d03 1482#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2 1483#define mmDSCL0_MPC_SIZE 0x0d04 1484#define mmDSCL0_MPC_SIZE_BASE_IDX 2 1485#define mmDSCL0_LB_DATA_FORMAT 0x0d05 1486#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2 1487#define mmDSCL0_LB_MEMORY_CTRL 0x0d06 1488#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 1489#define mmDSCL0_LB_V_COUNTER 0x0d07 1490#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2 1491#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d08 1492#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 1493#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d09 1494#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 1495#define mmDSCL0_OBUF_CONTROL 0x0d0a 1496#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2 1497#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d0b 1498#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 1499 1500 1501// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 1502// base address: 0x0 1503#define mmCM0_CM_CONTROL 0x0d1a 1504#define mmCM0_CM_CONTROL_BASE_IDX 2 1505#define mmCM0_CM_ICSC_CONTROL 0x0d1b 1506#define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2 1507#define mmCM0_CM_ICSC_C11_C12 0x0d1c 1508#define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2 1509#define mmCM0_CM_ICSC_C13_C14 0x0d1d 1510#define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2 1511#define mmCM0_CM_ICSC_C21_C22 0x0d1e 1512#define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2 1513#define mmCM0_CM_ICSC_C23_C24 0x0d1f 1514#define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2 1515#define mmCM0_CM_ICSC_C31_C32 0x0d20 1516#define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2 1517#define mmCM0_CM_ICSC_C33_C34 0x0d21 1518#define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2 1519#define mmCM0_CM_ICSC_B_C11_C12 0x0d22 1520#define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX 2 1521#define mmCM0_CM_ICSC_B_C13_C14 0x0d23 1522#define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX 2 1523#define mmCM0_CM_ICSC_B_C21_C22 0x0d24 1524#define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX 2 1525#define mmCM0_CM_ICSC_B_C23_C24 0x0d25 1526#define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX 2 1527#define mmCM0_CM_ICSC_B_C31_C32 0x0d26 1528#define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX 2 1529#define mmCM0_CM_ICSC_B_C33_C34 0x0d27 1530#define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX 2 1531#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d28 1532#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 1533#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d29 1534#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 1535#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d2a 1536#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 1537#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d2b 1538#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 1539#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d2c 1540#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 1541#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d2d 1542#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 1543#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d2e 1544#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 1545#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d2f 1546#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 1547#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d30 1548#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 1549#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d31 1550#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 1551#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d32 1552#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 1553#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d33 1554#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 1555#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d34 1556#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 1557#define mmCM0_CM_BIAS_CR_R 0x0d35 1558#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2 1559#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d36 1560#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 1561#define mmCM0_CM_DGAM_CONTROL 0x0d37 1562#define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2 1563#define mmCM0_CM_DGAM_LUT_INDEX 0x0d38 1564#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2 1565#define mmCM0_CM_DGAM_LUT_DATA 0x0d39 1566#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2 1567#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0d3a 1568#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 1569#define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0d3b 1570#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 1571#define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0d3c 1572#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 1573#define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0d3d 1574#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 1575#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0d3e 1576#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 1577#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0d3f 1578#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 1579#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0d40 1580#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 1581#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0d41 1582#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 1583#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0d42 1584#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 1585#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0d43 1586#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 1587#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0d44 1588#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 1589#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0d45 1590#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 1591#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0d46 1592#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 1593#define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0d47 1594#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 1595#define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0d48 1596#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 1597#define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0d49 1598#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 1599#define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0d4a 1600#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 1601#define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0d4b 1602#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 1603#define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0d4c 1604#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 1605#define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0d4d 1606#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 1607#define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0d4e 1608#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 1609#define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0d4f 1610#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 1611#define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0d50 1612#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 1613#define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0d51 1614#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 1615#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0d52 1616#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 1617#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0d53 1618#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 1619#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0d54 1620#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 1621#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0d55 1622#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 1623#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0d56 1624#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 1625#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0d57 1626#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 1627#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0d58 1628#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 1629#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0d59 1630#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 1631#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0d5a 1632#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 1633#define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0d5b 1634#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 1635#define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0d5c 1636#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 1637#define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0d5d 1638#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 1639#define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0d5e 1640#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 1641#define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0d5f 1642#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 1643#define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0d60 1644#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 1645#define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0d61 1646#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 1647#define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0d62 1648#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 1649#define mmCM0_CM_BLNDGAM_CONTROL 0x0d63 1650#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 1651#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d64 1652#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 1653#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d65 1654#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 1655#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0d66 1656#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 1657#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d67 1658#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 1659#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d68 1660#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 1661#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d69 1662#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 1663#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0d6a 1664#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 1665#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0d6b 1666#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 1667#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0d6c 1668#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 1669#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d6d 1670#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 1671#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d6e 1672#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 1673#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d6f 1674#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 1675#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d70 1676#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 1677#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d71 1678#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 1679#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d72 1680#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 1681#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d73 1682#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 1683#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d74 1684#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 1685#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d75 1686#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 1687#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0d76 1688#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 1689#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0d77 1690#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 1691#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0d78 1692#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 1693#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0d79 1694#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 1695#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0d7a 1696#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 1697#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0d7b 1698#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 1699#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0d7c 1700#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 1701#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0d7d 1702#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 1703#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0d7e 1704#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 1705#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0d7f 1706#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 1707#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0d80 1708#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 1709#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0d81 1710#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 1711#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0d82 1712#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 1713#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0d83 1714#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 1715#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0d84 1716#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 1717#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0d85 1718#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 1719#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0d86 1720#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 1721#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0d87 1722#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 1723#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0d88 1724#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 1725#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0d89 1726#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 1727#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0d8a 1728#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 1729#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0d8b 1730#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 1731#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0d8c 1732#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 1733#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0d8d 1734#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 1735#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0d8e 1736#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 1737#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0d8f 1738#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 1739#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0d90 1740#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 1741#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0d91 1742#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 1743#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0d92 1744#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 1745#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0d93 1746#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 1747#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0d94 1748#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 1749#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0d95 1750#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 1751#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0d96 1752#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 1753#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0d97 1754#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 1755#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0d98 1756#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 1757#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0d99 1758#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 1759#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0d9a 1760#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 1761#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0d9b 1762#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 1763#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0d9c 1764#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 1765#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0d9d 1766#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 1767#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0d9e 1768#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 1769#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0d9f 1770#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 1771#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0da0 1772#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 1773#define mmCM0_CM_HDR_MULT_COEF 0x0da1 1774#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2 1775#define mmCM0_CM_MEM_PWR_CTRL 0x0da2 1776#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 1777#define mmCM0_CM_MEM_PWR_STATUS 0x0da3 1778#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 1779#define mmCM0_CM_DEALPHA 0x0da5 1780#define mmCM0_CM_DEALPHA_BASE_IDX 2 1781#define mmCM0_CM_COEF_FORMAT 0x0da6 1782#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2 1783#define mmCM0_CM_SHAPER_CONTROL 0x0da7 1784#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2 1785#define mmCM0_CM_SHAPER_OFFSET_R 0x0da8 1786#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 1787#define mmCM0_CM_SHAPER_OFFSET_G 0x0da9 1788#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 1789#define mmCM0_CM_SHAPER_OFFSET_B 0x0daa 1790#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 1791#define mmCM0_CM_SHAPER_SCALE_R 0x0dab 1792#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 1793#define mmCM0_CM_SHAPER_SCALE_G_B 0x0dac 1794#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 1795#define mmCM0_CM_SHAPER_LUT_INDEX 0x0dad 1796#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 1797#define mmCM0_CM_SHAPER_LUT_DATA 0x0dae 1798#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 1799#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0daf 1800#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 1801#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0db0 1802#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 1803#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0db1 1804#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 1805#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0db2 1806#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 1807#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0db3 1808#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 1809#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0db4 1810#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 1811#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0db5 1812#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 1813#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0db6 1814#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 1815#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0db7 1816#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 1817#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0db8 1818#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 1819#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0db9 1820#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 1821#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dba 1822#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 1823#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0dbb 1824#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 1825#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dbc 1826#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 1827#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0dbd 1828#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 1829#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dbe 1830#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 1831#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0dbf 1832#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 1833#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0dc0 1834#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 1835#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0dc1 1836#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 1837#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0dc2 1838#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 1839#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0dc3 1840#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 1841#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0dc4 1842#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 1843#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0dc5 1844#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 1845#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0dc6 1846#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 1847#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0dc7 1848#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 1849#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0dc8 1850#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 1851#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0dc9 1852#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 1853#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dca 1854#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 1855#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dcb 1856#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 1857#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dcc 1858#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 1859#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dcd 1860#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 1861#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dce 1862#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 1863#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dcf 1864#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 1865#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0dd0 1866#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 1867#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0dd1 1868#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 1869#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0dd2 1870#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 1871#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0dd3 1872#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 1873#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0dd4 1874#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 1875#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0dd5 1876#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 1877#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0dd6 1878#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 1879#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0dd7 1880#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 1881#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0dd8 1882#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 1883#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0dd9 1884#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 1885#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0dda 1886#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 1887#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0ddb 1888#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 1889#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0ddc 1890#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 1891#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0ddd 1892#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 1893#define mmCM0_CM_MEM_PWR_CTRL2 0x0dde 1894#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 1895#define mmCM0_CM_MEM_PWR_STATUS2 0x0ddf 1896#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 1897#define mmCM0_CM_3DLUT_MODE 0x0de0 1898#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2 1899#define mmCM0_CM_3DLUT_INDEX 0x0de1 1900#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2 1901#define mmCM0_CM_3DLUT_DATA 0x0de2 1902#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2 1903#define mmCM0_CM_3DLUT_DATA_30BIT 0x0de3 1904#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 1905#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0de4 1906#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 1907#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0de5 1908#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 1909#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0de6 1910#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 1911#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0de7 1912#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 1913#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0de8 1914#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 1915#define mmCM0_CM_TEST_DEBUG_INDEX 0x0de9 1916#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 1917#define mmCM0_CM_TEST_DEBUG_DATA 0x0dea 1918#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 1919 1920// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 1921// base address: 0x5ac 1922#define mmDPP_TOP1_DPP_CONTROL 0x0e30 1923#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2 1924#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31 1925#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 1926#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 1927#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 1928#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 1929#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 1930#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34 1931#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 1932#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35 1933#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 1934 1935 1936// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 1937// base address: 0x5ac 1938#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 1939#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 1940#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b 1941#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 1942#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 1943#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 1944#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 1945#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 1946#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 1947#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 1948#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 1949#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 1950#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 1951#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 1952#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 1953#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 1954#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 1955#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 1956#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 1957#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 1958#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44 1959#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 1960#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 1961#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 1962#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 1963#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 1964#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 1965#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 1966 1967// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 1968// base address: 0x5ac 1969#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e4b 1970#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 1971#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e4c 1972#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 1973#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e4d 1974#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 1975#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e4e 1976#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 1977 1978 1979// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 1980// base address: 0x5ac 1981#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e55 1982#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 1983#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e56 1984#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 1985#define mmDSCL1_SCL_MODE 0x0e57 1986#define mmDSCL1_SCL_MODE_BASE_IDX 2 1987#define mmDSCL1_SCL_TAP_CONTROL 0x0e58 1988#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 1989#define mmDSCL1_DSCL_CONTROL 0x0e59 1990#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2 1991#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e5a 1992#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 1993#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e5b 1994#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 1995#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e5c 1996#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 1997#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e5d 1998#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 1999#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e5e 2000#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 2001#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e5f 2002#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 2003#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e60 2004#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 2005#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e61 2006#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 2007#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e62 2008#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 2009#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e63 2010#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 2011#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e64 2012#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 2013#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e65 2014#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 2015#define mmDSCL1_SCL_BLACK_OFFSET 0x0e66 2016#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2 2017#define mmDSCL1_DSCL_UPDATE 0x0e67 2018#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2 2019#define mmDSCL1_DSCL_AUTOCAL 0x0e68 2020#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2 2021#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e69 2022#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 2023#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e6a 2024#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 2025#define mmDSCL1_OTG_H_BLANK 0x0e6b 2026#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2 2027#define mmDSCL1_OTG_V_BLANK 0x0e6c 2028#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2 2029#define mmDSCL1_RECOUT_START 0x0e6d 2030#define mmDSCL1_RECOUT_START_BASE_IDX 2 2031#define mmDSCL1_RECOUT_SIZE 0x0e6e 2032#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2 2033#define mmDSCL1_MPC_SIZE 0x0e6f 2034#define mmDSCL1_MPC_SIZE_BASE_IDX 2 2035#define mmDSCL1_LB_DATA_FORMAT 0x0e70 2036#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2 2037#define mmDSCL1_LB_MEMORY_CTRL 0x0e71 2038#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 2039#define mmDSCL1_LB_V_COUNTER 0x0e72 2040#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2 2041#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e73 2042#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 2043#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e74 2044#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 2045#define mmDSCL1_OBUF_CONTROL 0x0e75 2046#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2 2047#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e76 2048#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 2049 2050 2051// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 2052// base address: 0x5ac 2053#define mmCM1_CM_CONTROL 0x0e85 2054#define mmCM1_CM_CONTROL_BASE_IDX 2 2055#define mmCM1_CM_ICSC_CONTROL 0x0e86 2056#define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2 2057#define mmCM1_CM_ICSC_C11_C12 0x0e87 2058#define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2 2059#define mmCM1_CM_ICSC_C13_C14 0x0e88 2060#define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2 2061#define mmCM1_CM_ICSC_C21_C22 0x0e89 2062#define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2 2063#define mmCM1_CM_ICSC_C23_C24 0x0e8a 2064#define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2 2065#define mmCM1_CM_ICSC_C31_C32 0x0e8b 2066#define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2 2067#define mmCM1_CM_ICSC_C33_C34 0x0e8c 2068#define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2 2069#define mmCM1_CM_ICSC_B_C11_C12 0x0e8d 2070#define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX 2 2071#define mmCM1_CM_ICSC_B_C13_C14 0x0e8e 2072#define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX 2 2073#define mmCM1_CM_ICSC_B_C21_C22 0x0e8f 2074#define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX 2 2075#define mmCM1_CM_ICSC_B_C23_C24 0x0e90 2076#define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX 2 2077#define mmCM1_CM_ICSC_B_C31_C32 0x0e91 2078#define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX 2 2079#define mmCM1_CM_ICSC_B_C33_C34 0x0e92 2080#define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX 2 2081#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e93 2082#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 2083#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e94 2084#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 2085#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e95 2086#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 2087#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e96 2088#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 2089#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e97 2090#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 2091#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e98 2092#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 2093#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e99 2094#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 2095#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0e9a 2096#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 2097#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0e9b 2098#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 2099#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0e9c 2100#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 2101#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0e9d 2102#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 2103#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0e9e 2104#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 2105#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0e9f 2106#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 2107#define mmCM1_CM_BIAS_CR_R 0x0ea0 2108#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2 2109#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea1 2110#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 2111#define mmCM1_CM_DGAM_CONTROL 0x0ea2 2112#define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2 2113#define mmCM1_CM_DGAM_LUT_INDEX 0x0ea3 2114#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2 2115#define mmCM1_CM_DGAM_LUT_DATA 0x0ea4 2116#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2 2117#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ea5 2118#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 2119#define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0ea6 2120#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 2121#define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0ea7 2122#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 2123#define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0ea8 2124#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 2125#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0ea9 2126#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 2127#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eaa 2128#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 2129#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0eab 2130#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 2131#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0eac 2132#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 2133#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0ead 2134#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 2135#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0eae 2136#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 2137#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0eaf 2138#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 2139#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0eb0 2140#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 2141#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0eb1 2142#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 2143#define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0eb2 2144#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 2145#define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0eb3 2146#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 2147#define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0eb4 2148#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 2149#define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0eb5 2150#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 2151#define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0eb6 2152#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 2153#define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0eb7 2154#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 2155#define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0eb8 2156#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 2157#define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0eb9 2158#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 2159#define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0eba 2160#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 2161#define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0ebb 2162#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 2163#define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0ebc 2164#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 2165#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0ebd 2166#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 2167#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0ebe 2168#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 2169#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0ebf 2170#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 2171#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0ec0 2172#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 2173#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0ec1 2174#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 2175#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0ec2 2176#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 2177#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0ec3 2178#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 2179#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0ec4 2180#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 2181#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0ec5 2182#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 2183#define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0ec6 2184#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 2185#define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0ec7 2186#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 2187#define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0ec8 2188#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 2189#define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0ec9 2190#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 2191#define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0eca 2192#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 2193#define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0ecb 2194#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 2195#define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0ecc 2196#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 2197#define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0ecd 2198#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 2199#define mmCM1_CM_BLNDGAM_CONTROL 0x0ece 2200#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 2201#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ecf 2202#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 2203#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ed0 2204#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 2205#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0ed1 2206#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 2207#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ed2 2208#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 2209#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ed3 2210#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 2211#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ed4 2212#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 2213#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0ed5 2214#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 2215#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0ed6 2216#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 2217#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0ed7 2218#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 2219#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0ed8 2220#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 2221#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0ed9 2222#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 2223#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0eda 2224#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 2225#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0edb 2226#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 2227#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0edc 2228#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 2229#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0edd 2230#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 2231#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0ede 2232#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 2233#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0edf 2234#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 2235#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0ee0 2236#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 2237#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0ee1 2238#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 2239#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0ee2 2240#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 2241#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0ee3 2242#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 2243#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0ee4 2244#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 2245#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0ee5 2246#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 2247#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0ee6 2248#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 2249#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0ee7 2250#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 2251#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0ee8 2252#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 2253#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0ee9 2254#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 2255#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0eea 2256#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 2257#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0eeb 2258#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 2259#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0eec 2260#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 2261#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0eed 2262#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 2263#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0eee 2264#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 2265#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0eef 2266#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 2267#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0ef0 2268#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 2269#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0ef1 2270#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 2271#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0ef2 2272#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 2273#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0ef3 2274#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 2275#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0ef4 2276#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 2277#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0ef5 2278#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 2279#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0ef6 2280#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 2281#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0ef7 2282#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 2283#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0ef8 2284#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 2285#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0ef9 2286#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 2287#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0efa 2288#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 2289#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0efb 2290#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 2291#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0efc 2292#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 2293#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0efd 2294#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 2295#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0efe 2296#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 2297#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0eff 2298#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 2299#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f00 2300#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 2301#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f01 2302#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 2303#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f02 2304#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 2305#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f03 2306#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 2307#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f04 2308#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 2309#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f05 2310#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 2311#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f06 2312#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 2313#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f07 2314#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 2315#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f08 2316#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 2317#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f09 2318#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 2319#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f0a 2320#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 2321#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f0b 2322#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 2323#define mmCM1_CM_HDR_MULT_COEF 0x0f0c 2324#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2 2325#define mmCM1_CM_MEM_PWR_CTRL 0x0f0d 2326#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 2327#define mmCM1_CM_MEM_PWR_STATUS 0x0f0e 2328#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 2329#define mmCM1_CM_DEALPHA 0x0f10 2330#define mmCM1_CM_DEALPHA_BASE_IDX 2 2331#define mmCM1_CM_COEF_FORMAT 0x0f11 2332#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2 2333#define mmCM1_CM_SHAPER_CONTROL 0x0f12 2334#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2 2335#define mmCM1_CM_SHAPER_OFFSET_R 0x0f13 2336#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 2337#define mmCM1_CM_SHAPER_OFFSET_G 0x0f14 2338#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 2339#define mmCM1_CM_SHAPER_OFFSET_B 0x0f15 2340#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 2341#define mmCM1_CM_SHAPER_SCALE_R 0x0f16 2342#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 2343#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f17 2344#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 2345#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f18 2346#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 2347#define mmCM1_CM_SHAPER_LUT_DATA 0x0f19 2348#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 2349#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f1a 2350#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 2351#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f1b 2352#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 2353#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f1c 2354#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 2355#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f1d 2356#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 2357#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f1e 2358#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 2359#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f1f 2360#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 2361#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f20 2362#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 2363#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f21 2364#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 2365#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f22 2366#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 2367#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f23 2368#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 2369#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f24 2370#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 2371#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f25 2372#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 2373#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f26 2374#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 2375#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f27 2376#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 2377#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f28 2378#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 2379#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f29 2380#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 2381#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f2a 2382#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 2383#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f2b 2384#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 2385#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f2c 2386#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 2387#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f2d 2388#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 2389#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f2e 2390#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 2391#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f2f 2392#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 2393#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f30 2394#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 2395#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f31 2396#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 2397#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f32 2398#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 2399#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f33 2400#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 2401#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f34 2402#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 2403#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f35 2404#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 2405#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f36 2406#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 2407#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f37 2408#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 2409#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f38 2410#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 2411#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f39 2412#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 2413#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f3a 2414#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 2415#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f3b 2416#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 2417#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f3c 2418#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 2419#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f3d 2420#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 2421#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f3e 2422#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 2423#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f3f 2424#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 2425#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f40 2426#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 2427#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f41 2428#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 2429#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f42 2430#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 2431#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f43 2432#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 2433#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f44 2434#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 2435#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f45 2436#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 2437#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f46 2438#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 2439#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f47 2440#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 2441#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f48 2442#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 2443#define mmCM1_CM_MEM_PWR_CTRL2 0x0f49 2444#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 2445#define mmCM1_CM_MEM_PWR_STATUS2 0x0f4a 2446#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 2447#define mmCM1_CM_3DLUT_MODE 0x0f4b 2448#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2 2449#define mmCM1_CM_3DLUT_INDEX 0x0f4c 2450#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2 2451#define mmCM1_CM_3DLUT_DATA 0x0f4d 2452#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2 2453#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f4e 2454#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 2455#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f4f 2456#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 2457#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f50 2458#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 2459#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f51 2460#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 2461#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f52 2462#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 2463#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f53 2464#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 2465#define mmCM1_CM_TEST_DEBUG_INDEX 0x0f54 2466#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 2467#define mmCM1_CM_TEST_DEBUG_DATA 0x0f55 2468#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 2469 2470 2471// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 2472// base address: 0xb58 2473#define mmDPP_TOP2_DPP_CONTROL 0x0f9b 2474#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2 2475#define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c 2476#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 2477#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 2478#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 2479#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 2480#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 2481#define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f 2482#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 2483 2484// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 2485// base address: 0xb58 2486#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 2487#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 2488#define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6 2489#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 2490#define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 2491#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 2492#define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 2493#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 2494#define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 2495#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 2496#define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 2497#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 2498#define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 2499#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 2500#define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 2501#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 2502#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 2503#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 2504#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 2505#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 2506#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf 2507#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 2508#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 2509#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 2510#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 2511#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 2512#define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 2513#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 2514 2515 2516// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 2517// base address: 0xb58 2518#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fb6 2519#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 2520#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fb7 2521#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 2522#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fb8 2523#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 2524#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fb9 2525#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 2526 2527 2528// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 2529// base address: 0xb58 2530#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fc0 2531#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 2532#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fc1 2533#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 2534#define mmDSCL2_SCL_MODE 0x0fc2 2535#define mmDSCL2_SCL_MODE_BASE_IDX 2 2536#define mmDSCL2_SCL_TAP_CONTROL 0x0fc3 2537#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 2538#define mmDSCL2_DSCL_CONTROL 0x0fc4 2539#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2 2540#define mmDSCL2_DSCL_2TAP_CONTROL 0x0fc5 2541#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 2542#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fc6 2543#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 2544#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fc7 2545#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 2546#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fc8 2547#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 2548#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fc9 2549#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 2550#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fca 2551#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 2552#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fcb 2553#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 2554#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fcc 2555#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 2556#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fcd 2557#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 2558#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fce 2559#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 2560#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fcf 2561#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 2562#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fd0 2563#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 2564#define mmDSCL2_SCL_BLACK_OFFSET 0x0fd1 2565#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2 2566#define mmDSCL2_DSCL_UPDATE 0x0fd2 2567#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2 2568#define mmDSCL2_DSCL_AUTOCAL 0x0fd3 2569#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2 2570#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fd4 2571#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 2572#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fd5 2573#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 2574#define mmDSCL2_OTG_H_BLANK 0x0fd6 2575#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2 2576#define mmDSCL2_OTG_V_BLANK 0x0fd7 2577#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2 2578#define mmDSCL2_RECOUT_START 0x0fd8 2579#define mmDSCL2_RECOUT_START_BASE_IDX 2 2580#define mmDSCL2_RECOUT_SIZE 0x0fd9 2581#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2 2582#define mmDSCL2_MPC_SIZE 0x0fda 2583#define mmDSCL2_MPC_SIZE_BASE_IDX 2 2584#define mmDSCL2_LB_DATA_FORMAT 0x0fdb 2585#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2 2586#define mmDSCL2_LB_MEMORY_CTRL 0x0fdc 2587#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 2588#define mmDSCL2_LB_V_COUNTER 0x0fdd 2589#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2 2590#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fde 2591#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 2592#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fdf 2593#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 2594#define mmDSCL2_OBUF_CONTROL 0x0fe0 2595#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2 2596#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0fe1 2597#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 2598 2599 2600// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 2601// base address: 0xb58 2602#define mmCM2_CM_CONTROL 0x0ff0 2603#define mmCM2_CM_CONTROL_BASE_IDX 2 2604#define mmCM2_CM_ICSC_CONTROL 0x0ff1 2605#define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2 2606#define mmCM2_CM_ICSC_C11_C12 0x0ff2 2607#define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2 2608#define mmCM2_CM_ICSC_C13_C14 0x0ff3 2609#define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2 2610#define mmCM2_CM_ICSC_C21_C22 0x0ff4 2611#define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2 2612#define mmCM2_CM_ICSC_C23_C24 0x0ff5 2613#define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2 2614#define mmCM2_CM_ICSC_C31_C32 0x0ff6 2615#define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2 2616#define mmCM2_CM_ICSC_C33_C34 0x0ff7 2617#define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2 2618#define mmCM2_CM_ICSC_B_C11_C12 0x0ff8 2619#define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX 2 2620#define mmCM2_CM_ICSC_B_C13_C14 0x0ff9 2621#define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX 2 2622#define mmCM2_CM_ICSC_B_C21_C22 0x0ffa 2623#define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX 2 2624#define mmCM2_CM_ICSC_B_C23_C24 0x0ffb 2625#define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX 2 2626#define mmCM2_CM_ICSC_B_C31_C32 0x0ffc 2627#define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX 2 2628#define mmCM2_CM_ICSC_B_C33_C34 0x0ffd 2629#define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX 2 2630#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ffe 2631#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 2632#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0fff 2633#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 2634#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1000 2635#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 2636#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1001 2637#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 2638#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1002 2639#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 2640#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1003 2641#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 2642#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x1004 2643#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 2644#define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x1005 2645#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 2646#define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x1006 2647#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 2648#define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x1007 2649#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 2650#define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x1008 2651#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 2652#define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x1009 2653#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 2654#define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x100a 2655#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 2656#define mmCM2_CM_BIAS_CR_R 0x100b 2657#define mmCM2_CM_BIAS_CR_R_BASE_IDX 2 2658#define mmCM2_CM_BIAS_Y_G_CB_B 0x100c 2659#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 2660#define mmCM2_CM_DGAM_CONTROL 0x100d 2661#define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2 2662#define mmCM2_CM_DGAM_LUT_INDEX 0x100e 2663#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2 2664#define mmCM2_CM_DGAM_LUT_DATA 0x100f 2665#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2 2666#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x1010 2667#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 2668#define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x1011 2669#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 2670#define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x1012 2671#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 2672#define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x1013 2673#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 2674#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1014 2675#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 2676#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1015 2677#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 2678#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1016 2679#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 2680#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x1017 2681#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 2682#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x1018 2683#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 2684#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x1019 2685#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 2686#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x101a 2687#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 2688#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x101b 2689#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 2690#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x101c 2691#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 2692#define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x101d 2693#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 2694#define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x101e 2695#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 2696#define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x101f 2697#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 2698#define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x1020 2699#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 2700#define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x1021 2701#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 2702#define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x1022 2703#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 2704#define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x1023 2705#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 2706#define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x1024 2707#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 2708#define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x1025 2709#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 2710#define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x1026 2711#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 2712#define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x1027 2713#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 2714#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1028 2715#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 2716#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1029 2717#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 2718#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102a 2719#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 2720#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x102b 2721#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 2722#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x102c 2723#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 2724#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x102d 2725#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 2726#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x102e 2727#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 2728#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x102f 2729#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 2730#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x1030 2731#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 2732#define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x1031 2733#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 2734#define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x1032 2735#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 2736#define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x1033 2737#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 2738#define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x1034 2739#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 2740#define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x1035 2741#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 2742#define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x1036 2743#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 2744#define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x1037 2745#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 2746#define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x1038 2747#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 2748#define mmCM2_CM_BLNDGAM_CONTROL 0x1039 2749#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 2750#define mmCM2_CM_BLNDGAM_LUT_INDEX 0x103a 2751#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 2752#define mmCM2_CM_BLNDGAM_LUT_DATA 0x103b 2753#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 2754#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x103c 2755#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 2756#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x103d 2757#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 2758#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x103e 2759#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 2760#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x103f 2761#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 2762#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x1040 2763#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 2764#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x1041 2765#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 2766#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x1042 2767#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 2768#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1043 2769#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 2770#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1044 2771#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 2772#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1045 2773#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 2774#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1046 2775#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 2776#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1047 2777#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 2778#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1048 2779#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 2780#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1049 2781#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 2782#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x104a 2783#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 2784#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x104b 2785#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 2786#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x104c 2787#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 2788#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x104d 2789#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 2790#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x104e 2791#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 2792#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x104f 2793#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 2794#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x1050 2795#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 2796#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x1051 2797#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 2798#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x1052 2799#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 2800#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x1053 2801#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 2802#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x1054 2803#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 2804#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x1055 2805#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 2806#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1056 2807#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 2808#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1057 2809#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 2810#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1058 2811#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 2812#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1059 2813#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 2814#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x105a 2815#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 2816#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x105b 2817#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 2818#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x105c 2819#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 2820#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x105d 2821#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 2822#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x105e 2823#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 2824#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x105f 2825#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 2826#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1060 2827#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 2828#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1061 2829#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 2830#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1062 2831#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 2832#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1063 2833#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 2834#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1064 2835#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 2836#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1065 2837#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 2838#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1066 2839#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 2840#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1067 2841#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 2842#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1068 2843#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 2844#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1069 2845#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 2846#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x106a 2847#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 2848#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x106b 2849#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 2850#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x106c 2851#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 2852#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x106d 2853#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 2854#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x106e 2855#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 2856#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x106f 2857#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 2858#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x1070 2859#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 2860#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x1071 2861#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 2862#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x1072 2863#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 2864#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x1073 2865#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 2866#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x1074 2867#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 2868#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x1075 2869#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 2870#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x1076 2871#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 2872#define mmCM2_CM_HDR_MULT_COEF 0x1077 2873#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2 2874#define mmCM2_CM_MEM_PWR_CTRL 0x1078 2875#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 2876#define mmCM2_CM_MEM_PWR_STATUS 0x1079 2877#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 2878#define mmCM2_CM_DEALPHA 0x107b 2879#define mmCM2_CM_DEALPHA_BASE_IDX 2 2880#define mmCM2_CM_COEF_FORMAT 0x107c 2881#define mmCM2_CM_COEF_FORMAT_BASE_IDX 2 2882#define mmCM2_CM_SHAPER_CONTROL 0x107d 2883#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2 2884#define mmCM2_CM_SHAPER_OFFSET_R 0x107e 2885#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 2886#define mmCM2_CM_SHAPER_OFFSET_G 0x107f 2887#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 2888#define mmCM2_CM_SHAPER_OFFSET_B 0x1080 2889#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 2890#define mmCM2_CM_SHAPER_SCALE_R 0x1081 2891#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 2892#define mmCM2_CM_SHAPER_SCALE_G_B 0x1082 2893#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 2894#define mmCM2_CM_SHAPER_LUT_INDEX 0x1083 2895#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 2896#define mmCM2_CM_SHAPER_LUT_DATA 0x1084 2897#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 2898#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x1085 2899#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 2900#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x1086 2901#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 2902#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x1087 2903#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 2904#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x1088 2905#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 2906#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x1089 2907#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 2908#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x108a 2909#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 2910#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x108b 2911#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 2912#define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x108c 2913#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 2914#define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x108d 2915#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 2916#define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x108e 2917#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 2918#define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x108f 2919#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 2920#define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x1090 2921#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 2922#define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x1091 2923#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 2924#define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x1092 2925#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 2926#define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x1093 2927#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 2928#define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x1094 2929#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 2930#define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x1095 2931#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 2932#define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x1096 2933#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 2934#define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x1097 2935#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 2936#define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x1098 2937#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 2938#define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x1099 2939#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 2940#define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x109a 2941#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 2942#define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x109b 2943#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 2944#define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x109c 2945#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 2946#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x109d 2947#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 2948#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x109e 2949#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 2950#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x109f 2951#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 2952#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10a0 2953#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 2954#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10a1 2955#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 2956#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10a2 2957#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 2958#define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10a3 2959#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 2960#define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10a4 2961#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 2962#define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10a5 2963#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 2964#define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10a6 2965#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 2966#define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10a7 2967#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 2968#define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10a8 2969#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 2970#define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10a9 2971#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 2972#define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10aa 2973#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 2974#define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10ab 2975#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 2976#define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10ac 2977#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 2978#define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10ad 2979#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 2980#define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10ae 2981#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 2982#define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10af 2983#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 2984#define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10b0 2985#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 2986#define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10b1 2987#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 2988#define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10b2 2989#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 2990#define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10b3 2991#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 2992#define mmCM2_CM_MEM_PWR_CTRL2 0x10b4 2993#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 2994#define mmCM2_CM_MEM_PWR_STATUS2 0x10b5 2995#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 2996#define mmCM2_CM_3DLUT_MODE 0x10b6 2997#define mmCM2_CM_3DLUT_MODE_BASE_IDX 2 2998#define mmCM2_CM_3DLUT_INDEX 0x10b7 2999#define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2 3000#define mmCM2_CM_3DLUT_DATA 0x10b8 3001#define mmCM2_CM_3DLUT_DATA_BASE_IDX 2 3002#define mmCM2_CM_3DLUT_DATA_30BIT 0x10b9 3003#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 3004#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ba 3005#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 3006#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10bb 3007#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 3008#define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10bc 3009#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 3010#define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10bd 3011#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 3012#define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10be 3013#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 3014#define mmCM2_CM_TEST_DEBUG_INDEX 0x10bf 3015#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 3016#define mmCM2_CM_TEST_DEBUG_DATA 0x10c0 3017#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 3018 3019// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 3020// base address: 0x1104 3021#define mmDPP_TOP3_DPP_CONTROL 0x1106 3022#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2 3023#define mmDPP_TOP3_DPP_SOFT_RESET 0x1107 3024#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 3025#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 3026#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 3027#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 3028#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 3029#define mmDPP_TOP3_DPP_CRC_CTRL 0x110a 3030#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 3031 3032 3033// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 3034// base address: 0x1104 3035#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 3036#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3037#define mmCNVC_CFG3_FORMAT_CONTROL 0x1111 3038#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 3039#define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 3040#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 3041#define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 3042#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 3043#define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 3044#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 3045#define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 3046#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 3047#define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 3048#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 3049#define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 3050#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 3051#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 3052#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 3053#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 3054#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 3055#define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a 3056#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 3057#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 3058#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 3059#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 3060#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 3061#define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 3062#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 3063 3064 3065// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 3066// base address: 0x1104 3067#define mmCNVC_CUR3_CURSOR0_CONTROL 0x1121 3068#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 3069#define mmCNVC_CUR3_CURSOR0_COLOR0 0x1122 3070#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 3071#define mmCNVC_CUR3_CURSOR0_COLOR1 0x1123 3072#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 3073#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1124 3074#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3075 3076 3077// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 3078// base address: 0x1104 3079#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x112b 3080#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3081#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x112c 3082#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3083#define mmDSCL3_SCL_MODE 0x112d 3084#define mmDSCL3_SCL_MODE_BASE_IDX 2 3085#define mmDSCL3_SCL_TAP_CONTROL 0x112e 3086#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 3087#define mmDSCL3_DSCL_CONTROL 0x112f 3088#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2 3089#define mmDSCL3_DSCL_2TAP_CONTROL 0x1130 3090#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 3091#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1131 3092#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3093#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1132 3094#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3095#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1133 3096#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3097#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1134 3098#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3099#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1135 3100#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3101#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1136 3102#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3103#define mmDSCL3_SCL_VERT_FILTER_INIT 0x1137 3104#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 3105#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1138 3106#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3107#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1139 3108#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3109#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x113a 3110#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3111#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x113b 3112#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3113#define mmDSCL3_SCL_BLACK_OFFSET 0x113c 3114#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2 3115#define mmDSCL3_DSCL_UPDATE 0x113d 3116#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2 3117#define mmDSCL3_DSCL_AUTOCAL 0x113e 3118#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2 3119#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x113f 3120#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3121#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x1140 3122#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3123#define mmDSCL3_OTG_H_BLANK 0x1141 3124#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2 3125#define mmDSCL3_OTG_V_BLANK 0x1142 3126#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2 3127#define mmDSCL3_RECOUT_START 0x1143 3128#define mmDSCL3_RECOUT_START_BASE_IDX 2 3129#define mmDSCL3_RECOUT_SIZE 0x1144 3130#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2 3131#define mmDSCL3_MPC_SIZE 0x1145 3132#define mmDSCL3_MPC_SIZE_BASE_IDX 2 3133#define mmDSCL3_LB_DATA_FORMAT 0x1146 3134#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2 3135#define mmDSCL3_LB_MEMORY_CTRL 0x1147 3136#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 3137#define mmDSCL3_LB_V_COUNTER 0x1148 3138#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2 3139#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1149 3140#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3141#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x114a 3142#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3143#define mmDSCL3_OBUF_CONTROL 0x114b 3144#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2 3145#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x114c 3146#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3147 3148 3149// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 3150// base address: 0x1104 3151#define mmCM3_CM_CONTROL 0x115b 3152#define mmCM3_CM_CONTROL_BASE_IDX 2 3153#define mmCM3_CM_ICSC_CONTROL 0x115c 3154#define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2 3155#define mmCM3_CM_ICSC_C11_C12 0x115d 3156#define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2 3157#define mmCM3_CM_ICSC_C13_C14 0x115e 3158#define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2 3159#define mmCM3_CM_ICSC_C21_C22 0x115f 3160#define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2 3161#define mmCM3_CM_ICSC_C23_C24 0x1160 3162#define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2 3163#define mmCM3_CM_ICSC_C31_C32 0x1161 3164#define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2 3165#define mmCM3_CM_ICSC_C33_C34 0x1162 3166#define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2 3167#define mmCM3_CM_ICSC_B_C11_C12 0x1163 3168#define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX 2 3169#define mmCM3_CM_ICSC_B_C13_C14 0x1164 3170#define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX 2 3171#define mmCM3_CM_ICSC_B_C21_C22 0x1165 3172#define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX 2 3173#define mmCM3_CM_ICSC_B_C23_C24 0x1166 3174#define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX 2 3175#define mmCM3_CM_ICSC_B_C31_C32 0x1167 3176#define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX 2 3177#define mmCM3_CM_ICSC_B_C33_C34 0x1168 3178#define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX 2 3179#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1169 3180#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 3181#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x116a 3182#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 3183#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x116b 3184#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 3185#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x116c 3186#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 3187#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x116d 3188#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 3189#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x116e 3190#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 3191#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x116f 3192#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 3193#define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1170 3194#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 3195#define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1171 3196#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 3197#define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1172 3198#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 3199#define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1173 3200#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 3201#define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x1174 3202#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 3203#define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x1175 3204#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 3205#define mmCM3_CM_BIAS_CR_R 0x1176 3206#define mmCM3_CM_BIAS_CR_R_BASE_IDX 2 3207#define mmCM3_CM_BIAS_Y_G_CB_B 0x1177 3208#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 3209#define mmCM3_CM_DGAM_CONTROL 0x1178 3210#define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2 3211#define mmCM3_CM_DGAM_LUT_INDEX 0x1179 3212#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2 3213#define mmCM3_CM_DGAM_LUT_DATA 0x117a 3214#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2 3215#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x117b 3216#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 3217#define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x117c 3218#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 3219#define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x117d 3220#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 3221#define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x117e 3222#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 3223#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x117f 3224#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 3225#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1180 3226#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 3227#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1181 3228#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 3229#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x1182 3230#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 3231#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x1183 3232#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 3233#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x1184 3234#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 3235#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x1185 3236#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 3237#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1186 3238#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 3239#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1187 3240#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 3241#define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1188 3242#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 3243#define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1189 3244#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 3245#define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x118a 3246#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 3247#define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x118b 3248#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 3249#define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x118c 3250#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 3251#define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x118d 3252#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 3253#define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x118e 3254#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 3255#define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x118f 3256#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 3257#define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x1190 3258#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 3259#define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x1191 3260#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 3261#define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x1192 3262#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 3263#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1193 3264#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 3265#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1194 3266#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 3267#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x1195 3268#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 3269#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1196 3270#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 3271#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1197 3272#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 3273#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1198 3274#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 3275#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1199 3276#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 3277#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x119a 3278#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 3279#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x119b 3280#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 3281#define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x119c 3282#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 3283#define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x119d 3284#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 3285#define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x119e 3286#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 3287#define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x119f 3288#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 3289#define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x11a0 3290#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 3291#define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x11a1 3292#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 3293#define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x11a2 3294#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 3295#define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x11a3 3296#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 3297#define mmCM3_CM_BLNDGAM_CONTROL 0x11a4 3298#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 3299#define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11a5 3300#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 3301#define mmCM3_CM_BLNDGAM_LUT_DATA 0x11a6 3302#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 3303#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x11a7 3304#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 3305#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11a8 3306#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 3307#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11a9 3308#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 3309#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11aa 3310#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 3311#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x11ab 3312#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 3313#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x11ac 3314#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 3315#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x11ad 3316#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 3317#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11ae 3318#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 3319#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11af 3320#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 3321#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11b0 3322#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 3323#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11b1 3324#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 3325#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11b2 3326#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 3327#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11b3 3328#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 3329#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11b4 3330#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 3331#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11b5 3332#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 3333#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11b6 3334#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 3335#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11b7 3336#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 3337#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11b8 3338#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 3339#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11b9 3340#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 3341#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11ba 3342#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 3343#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11bb 3344#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 3345#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11bc 3346#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 3347#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11bd 3348#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 3349#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11be 3350#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 3351#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11bf 3352#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 3353#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11c0 3354#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 3355#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11c1 3356#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 3357#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11c2 3358#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 3359#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11c3 3360#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 3361#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11c4 3362#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 3363#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11c5 3364#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 3365#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11c6 3366#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 3367#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11c7 3368#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 3369#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x11c8 3370#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 3371#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x11c9 3372#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 3373#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x11ca 3374#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 3375#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11cb 3376#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 3377#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11cc 3378#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 3379#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11cd 3380#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 3381#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11ce 3382#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 3383#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11cf 3384#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 3385#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11d0 3386#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 3387#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x11d1 3388#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 3389#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x11d2 3390#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 3391#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x11d3 3392#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 3393#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x11d4 3394#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 3395#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x11d5 3396#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 3397#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x11d6 3398#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 3399#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x11d7 3400#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 3401#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x11d8 3402#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 3403#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x11d9 3404#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 3405#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x11da 3406#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 3407#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x11db 3408#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 3409#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x11dc 3410#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 3411#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x11dd 3412#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 3413#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x11de 3414#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 3415#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x11df 3416#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 3417#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x11e0 3418#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 3419#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x11e1 3420#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 3421#define mmCM3_CM_HDR_MULT_COEF 0x11e2 3422#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2 3423#define mmCM3_CM_MEM_PWR_CTRL 0x11e3 3424#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 3425#define mmCM3_CM_MEM_PWR_STATUS 0x11e4 3426#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 3427#define mmCM3_CM_DEALPHA 0x11e6 3428#define mmCM3_CM_DEALPHA_BASE_IDX 2 3429#define mmCM3_CM_COEF_FORMAT 0x11e7 3430#define mmCM3_CM_COEF_FORMAT_BASE_IDX 2 3431#define mmCM3_CM_SHAPER_CONTROL 0x11e8 3432#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2 3433#define mmCM3_CM_SHAPER_OFFSET_R 0x11e9 3434#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 3435#define mmCM3_CM_SHAPER_OFFSET_G 0x11ea 3436#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 3437#define mmCM3_CM_SHAPER_OFFSET_B 0x11eb 3438#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 3439#define mmCM3_CM_SHAPER_SCALE_R 0x11ec 3440#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 3441#define mmCM3_CM_SHAPER_SCALE_G_B 0x11ed 3442#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 3443#define mmCM3_CM_SHAPER_LUT_INDEX 0x11ee 3444#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 3445#define mmCM3_CM_SHAPER_LUT_DATA 0x11ef 3446#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 3447#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x11f0 3448#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 3449#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x11f1 3450#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 3451#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x11f2 3452#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 3453#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x11f3 3454#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 3455#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x11f4 3456#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 3457#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x11f5 3458#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 3459#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x11f6 3460#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 3461#define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x11f7 3462#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 3463#define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x11f8 3464#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 3465#define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x11f9 3466#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 3467#define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x11fa 3468#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 3469#define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x11fb 3470#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 3471#define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x11fc 3472#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 3473#define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x11fd 3474#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 3475#define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x11fe 3476#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 3477#define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x11ff 3478#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 3479#define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1200 3480#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 3481#define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1201 3482#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 3483#define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1202 3484#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 3485#define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1203 3486#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 3487#define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1204 3488#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 3489#define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1205 3490#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 3491#define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1206 3492#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 3493#define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1207 3494#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 3495#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1208 3496#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 3497#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1209 3498#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 3499#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x120a 3500#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 3501#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x120b 3502#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 3503#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x120c 3504#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 3505#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x120d 3506#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 3507#define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x120e 3508#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 3509#define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x120f 3510#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 3511#define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1210 3512#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 3513#define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1211 3514#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 3515#define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1212 3516#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 3517#define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1213 3518#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 3519#define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1214 3520#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 3521#define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1215 3522#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 3523#define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1216 3524#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 3525#define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1217 3526#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 3527#define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1218 3528#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 3529#define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1219 3530#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 3531#define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x121a 3532#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 3533#define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x121b 3534#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 3535#define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x121c 3536#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 3537#define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x121d 3538#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 3539#define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x121e 3540#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 3541#define mmCM3_CM_MEM_PWR_CTRL2 0x121f 3542#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 3543#define mmCM3_CM_MEM_PWR_STATUS2 0x1220 3544#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 3545#define mmCM3_CM_3DLUT_MODE 0x1221 3546#define mmCM3_CM_3DLUT_MODE_BASE_IDX 2 3547#define mmCM3_CM_3DLUT_INDEX 0x1222 3548#define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2 3549#define mmCM3_CM_3DLUT_DATA 0x1223 3550#define mmCM3_CM_3DLUT_DATA_BASE_IDX 2 3551#define mmCM3_CM_3DLUT_DATA_30BIT 0x1224 3552#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 3553#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1225 3554#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 3555#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1226 3556#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 3557#define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1227 3558#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 3559#define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1228 3560#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 3561#define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1229 3562#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 3563#define mmCM3_CM_TEST_DEBUG_INDEX 0x122a 3564#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 3565#define mmCM3_CM_TEST_DEBUG_DATA 0x122b 3566#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 3567 3568 3569// addressBlock: dce_dc_mpc_mpcc0_dispdec 3570// base address: 0x0 3571#define mmMPCC0_MPCC_TOP_SEL 0x1271 3572#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2 3573#define mmMPCC0_MPCC_BOT_SEL 0x1272 3574#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2 3575#define mmMPCC0_MPCC_OPP_ID 0x1273 3576#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2 3577#define mmMPCC0_MPCC_CONTROL 0x1274 3578#define mmMPCC0_MPCC_CONTROL_BASE_IDX 2 3579#define mmMPCC0_MPCC_SM_CONTROL 0x1275 3580#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2 3581#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1276 3582#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 3583#define mmMPCC0_MPCC_TOP_GAIN 0x1277 3584#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 2 3585#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x1278 3586#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 3587#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x1279 3588#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 3589#define mmMPCC0_MPCC_BG_R_CR 0x127a 3590#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2 3591#define mmMPCC0_MPCC_BG_G_Y 0x127b 3592#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2 3593#define mmMPCC0_MPCC_BG_B_CB 0x127c 3594#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2 3595#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x127d 3596#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 2 3597#define mmMPCC0_MPCC_STALL_STATUS 0x127e 3598#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2 3599#define mmMPCC0_MPCC_STATUS 0x127f 3600#define mmMPCC0_MPCC_STATUS_BASE_IDX 2 3601 3602 3603// addressBlock: dce_dc_mpc_mpcc1_dispdec 3604// base address: 0x6c 3605#define mmMPCC1_MPCC_TOP_SEL 0x128c 3606#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2 3607#define mmMPCC1_MPCC_BOT_SEL 0x128d 3608#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2 3609#define mmMPCC1_MPCC_OPP_ID 0x128e 3610#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2 3611#define mmMPCC1_MPCC_CONTROL 0x128f 3612#define mmMPCC1_MPCC_CONTROL_BASE_IDX 2 3613#define mmMPCC1_MPCC_SM_CONTROL 0x1290 3614#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2 3615#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1291 3616#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 3617#define mmMPCC1_MPCC_TOP_GAIN 0x1292 3618#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 2 3619#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x1293 3620#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 3621#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x1294 3622#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 3623#define mmMPCC1_MPCC_BG_R_CR 0x1295 3624#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2 3625#define mmMPCC1_MPCC_BG_G_Y 0x1296 3626#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2 3627#define mmMPCC1_MPCC_BG_B_CB 0x1297 3628#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2 3629#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x1298 3630#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 2 3631#define mmMPCC1_MPCC_STALL_STATUS 0x1299 3632#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2 3633#define mmMPCC1_MPCC_STATUS 0x129a 3634#define mmMPCC1_MPCC_STATUS_BASE_IDX 2 3635 3636 3637// addressBlock: dce_dc_mpc_mpcc2_dispdec 3638// base address: 0xd8 3639#define mmMPCC2_MPCC_TOP_SEL 0x12a7 3640#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2 3641#define mmMPCC2_MPCC_BOT_SEL 0x12a8 3642#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2 3643#define mmMPCC2_MPCC_OPP_ID 0x12a9 3644#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2 3645#define mmMPCC2_MPCC_CONTROL 0x12aa 3646#define mmMPCC2_MPCC_CONTROL_BASE_IDX 2 3647#define mmMPCC2_MPCC_SM_CONTROL 0x12ab 3648#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2 3649#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x12ac 3650#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 3651#define mmMPCC2_MPCC_TOP_GAIN 0x12ad 3652#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 2 3653#define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x12ae 3654#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 3655#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x12af 3656#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 3657#define mmMPCC2_MPCC_BG_R_CR 0x12b0 3658#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2 3659#define mmMPCC2_MPCC_BG_G_Y 0x12b1 3660#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2 3661#define mmMPCC2_MPCC_BG_B_CB 0x12b2 3662#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2 3663#define mmMPCC2_MPCC_MEM_PWR_CTRL 0x12b3 3664#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 2 3665#define mmMPCC2_MPCC_STALL_STATUS 0x12b4 3666#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2 3667#define mmMPCC2_MPCC_STATUS 0x12b5 3668#define mmMPCC2_MPCC_STATUS_BASE_IDX 2 3669 3670 3671// addressBlock: dce_dc_mpc_mpcc3_dispdec 3672// base address: 0x144 3673#define mmMPCC3_MPCC_TOP_SEL 0x12c2 3674#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2 3675#define mmMPCC3_MPCC_BOT_SEL 0x12c3 3676#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2 3677#define mmMPCC3_MPCC_OPP_ID 0x12c4 3678#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2 3679#define mmMPCC3_MPCC_CONTROL 0x12c5 3680#define mmMPCC3_MPCC_CONTROL_BASE_IDX 2 3681#define mmMPCC3_MPCC_SM_CONTROL 0x12c6 3682#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2 3683#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x12c7 3684#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 3685#define mmMPCC3_MPCC_TOP_GAIN 0x12c8 3686#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 2 3687#define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x12c9 3688#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 3689#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x12ca 3690#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 3691#define mmMPCC3_MPCC_BG_R_CR 0x12cb 3692#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2 3693#define mmMPCC3_MPCC_BG_G_Y 0x12cc 3694#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2 3695#define mmMPCC3_MPCC_BG_B_CB 0x12cd 3696#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2 3697#define mmMPCC3_MPCC_MEM_PWR_CTRL 0x12ce 3698#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 2 3699#define mmMPCC3_MPCC_STALL_STATUS 0x12cf 3700#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2 3701#define mmMPCC3_MPCC_STATUS 0x12d0 3702#define mmMPCC3_MPCC_STATUS_BASE_IDX 2 3703 3704// addressBlock: dce_dc_mpc_mpcc4_dispdec 3705// base address: 0x1b0 3706#define mmMPCC4_MPCC_TOP_SEL 0x12dd 3707#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 2 3708#define mmMPCC4_MPCC_BOT_SEL 0x12de 3709#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 2 3710#define mmMPCC4_MPCC_OPP_ID 0x12df 3711#define mmMPCC4_MPCC_OPP_ID_BASE_IDX 2 3712#define mmMPCC4_MPCC_CONTROL 0x12e0 3713#define mmMPCC4_MPCC_CONTROL_BASE_IDX 2 3714#define mmMPCC4_MPCC_SM_CONTROL 0x12e1 3715#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 2 3716#define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x12e2 3717#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 3718#define mmMPCC4_MPCC_TOP_GAIN 0x12e3 3719#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 2 3720#define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x12e4 3721#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 3722#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x12e5 3723#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 3724#define mmMPCC4_MPCC_BG_R_CR 0x12e6 3725#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 2 3726#define mmMPCC4_MPCC_BG_G_Y 0x12e7 3727#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 2 3728#define mmMPCC4_MPCC_BG_B_CB 0x12e8 3729#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 2 3730#define mmMPCC4_MPCC_MEM_PWR_CTRL 0x12e9 3731#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 2 3732#define mmMPCC4_MPCC_STALL_STATUS 0x12ea 3733#define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX 2 3734#define mmMPCC4_MPCC_STATUS 0x12eb 3735#define mmMPCC4_MPCC_STATUS_BASE_IDX 2 3736 3737 3738// addressBlock: dce_dc_mpc_mpc_cfg_dispdec 3739// base address: 0x0 3740#define mmMPC_CLOCK_CONTROL 0x1349 3741#define mmMPC_CLOCK_CONTROL_BASE_IDX 2 3742#define mmMPC_SOFT_RESET 0x134a 3743#define mmMPC_SOFT_RESET_BASE_IDX 2 3744#define mmMPC_CRC_CTRL 0x134b 3745#define mmMPC_CRC_CTRL_BASE_IDX 2 3746#define mmMPC_CRC_SEL_CONTROL 0x134c 3747#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2 3748#define mmMPC_CRC_RESULT_AR 0x134d 3749#define mmMPC_CRC_RESULT_AR_BASE_IDX 2 3750#define mmMPC_CRC_RESULT_GB 0x134e 3751#define mmMPC_CRC_RESULT_GB_BASE_IDX 2 3752#define mmMPC_CRC_RESULT_C 0x134f 3753#define mmMPC_CRC_RESULT_C_BASE_IDX 2 3754#define mmMPC_PERFMON_EVENT_CTRL 0x1352 3755#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2 3756#define mmMPC_BYPASS_BG_AR 0x1353 3757#define mmMPC_BYPASS_BG_AR_BASE_IDX 2 3758#define mmMPC_BYPASS_BG_GB 0x1354 3759#define mmMPC_BYPASS_BG_GB_BASE_IDX 2 3760#define mmMPC_STALL_GRACE_WINDOW 0x1355 3761#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2 3762#define mmMPC_HOST_READ_CONTROL 0x1356 3763#define mmMPC_HOST_READ_CONTROL_BASE_IDX 2 3764#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x135d 3765#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 2 3766#define mmADR_CFG_VUPDATE_LOCK_SET0 0x135e 3767#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2 3768#define mmADR_VUPDATE_LOCK_SET0 0x135f 3769#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2 3770#define mmCFG_VUPDATE_LOCK_SET0 0x1360 3771#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 2 3772#define mmCUR_VUPDATE_LOCK_SET0 0x1361 3773#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 2 3774#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x1362 3775#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 2 3776#define mmADR_CFG_VUPDATE_LOCK_SET1 0x1363 3777#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2 3778#define mmADR_VUPDATE_LOCK_SET1 0x1364 3779#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2 3780#define mmCFG_VUPDATE_LOCK_SET1 0x1365 3781#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 2 3782#define mmCUR_VUPDATE_LOCK_SET1 0x1366 3783#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 2 3784#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x1367 3785#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 2 3786#define mmADR_CFG_VUPDATE_LOCK_SET2 0x1368 3787#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2 3788#define mmADR_VUPDATE_LOCK_SET2 0x1369 3789#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2 3790#define mmCFG_VUPDATE_LOCK_SET2 0x136a 3791#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 2 3792#define mmCUR_VUPDATE_LOCK_SET2 0x136b 3793#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 2 3794#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x136c 3795#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 2 3796#define mmADR_CFG_VUPDATE_LOCK_SET3 0x136d 3797#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2 3798#define mmADR_VUPDATE_LOCK_SET3 0x136e 3799#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2 3800#define mmCFG_VUPDATE_LOCK_SET3 0x136f 3801#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 2 3802#define mmCUR_VUPDATE_LOCK_SET3 0x1370 3803#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 2 3804#define mmMPC_OUT0_MUX 0x1385 3805#define mmMPC_OUT0_MUX_BASE_IDX 2 3806#define mmMPC_OUT0_DENORM_CONTROL 0x1386 3807#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 2 3808#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x1387 3809#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 2 3810#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x1388 3811#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 2 3812#define mmMPC_OUT1_MUX 0x1389 3813#define mmMPC_OUT1_MUX_BASE_IDX 2 3814#define mmMPC_OUT1_DENORM_CONTROL 0x138a 3815#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 2 3816#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x138b 3817#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 2 3818#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x138c 3819#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 2 3820 3821 3822// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 3823// base address: 0x0 3824#define mmMPCC_OGAM0_MPCC_OGAM_MODE 0x13ae 3825#define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX 2 3826#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x13af 3827#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 3828#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x13b0 3829#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 2 3830#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL 0x13b1 3831#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 3832#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x13b2 3833#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 3834#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x13b3 3835#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 3836#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x13b4 3837#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 3838#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13b5 3839#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 3840#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13b6 3841#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 3842#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13b7 3843#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 3844#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x13b8 3845#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 3846#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x13b9 3847#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 3848#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x13ba 3849#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 3850#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x13bb 3851#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 3852#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x13bc 3853#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 3854#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x13bd 3855#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 3856#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x13be 3857#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 3858#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x13bf 3859#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 3860#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x13c0 3861#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 3862#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x13c1 3863#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 3864#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x13c2 3865#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 3866#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x13c3 3867#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 3868#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x13c4 3869#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 3870#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x13c5 3871#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 3872#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x13c6 3873#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 3874#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x13c7 3875#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 3876#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x13c8 3877#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 3878#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x13c9 3879#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 3880#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x13ca 3881#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 3882#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x13cb 3883#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 3884#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x13cc 3885#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 3886#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x13cd 3887#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 3888#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x13ce 3889#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 3890#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x13cf 3891#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 3892#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x13d0 3893#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 3894#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x13d1 3895#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 3896#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x13d2 3897#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 3898#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x13d3 3899#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 3900#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x13d4 3901#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 3902#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x13d5 3903#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 3904#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x13d6 3905#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 3906#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x13d7 3907#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 3908#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x13d8 3909#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 3910#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x13d9 3911#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 3912#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x13da 3913#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 3914#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x13db 3915#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 3916#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x13dc 3917#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 3918#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x13dd 3919#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 3920#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x13de 3921#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 3922#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x13df 3923#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 3924#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x13e0 3925#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 3926#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x13e1 3927#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 3928#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x13e2 3929#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 3930#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x13e3 3931#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 3932#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x13e4 3933#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 3934#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x13e5 3935#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 3936#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x13e6 3937#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 3938#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x13e7 3939#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 3940#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x13e8 3941#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 3942#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x13e9 3943#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 3944#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x13ea 3945#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 3946#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x13eb 3947#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 3948 3949 3950// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 3951// base address: 0x104 3952#define mmMPCC_OGAM1_MPCC_OGAM_MODE 0x13ef 3953#define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX 2 3954#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x13f0 3955#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 3956#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x13f1 3957#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 2 3958#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL 0x13f2 3959#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 3960#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x13f3 3961#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 3962#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x13f4 3963#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 3964#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x13f5 3965#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 3966#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13f6 3967#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 3968#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13f7 3969#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 3970#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13f8 3971#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 3972#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x13f9 3973#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 3974#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x13fa 3975#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 3976#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x13fb 3977#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 3978#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x13fc 3979#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 3980#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x13fd 3981#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 3982#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x13fe 3983#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 3984#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x13ff 3985#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 3986#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x1400 3987#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 3988#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x1401 3989#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 3990#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x1402 3991#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 3992#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x1403 3993#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 3994#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x1404 3995#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 3996#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x1405 3997#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 3998#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x1406 3999#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 4000#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x1407 4001#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 4002#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x1408 4003#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 4004#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x1409 4005#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 4006#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x140a 4007#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 4008#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x140b 4009#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 4010#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x140c 4011#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 4012#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x140d 4013#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 4014#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x140e 4015#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 4016#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x140f 4017#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 4018#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x1410 4019#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 4020#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x1411 4021#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 4022#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x1412 4023#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 4024#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1413 4025#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 4026#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1414 4027#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 4028#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1415 4029#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 4030#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x1416 4031#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4032#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x1417 4033#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4034#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x1418 4035#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4036#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x1419 4037#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4038#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x141a 4039#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4040#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x141b 4041#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4042#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x141c 4043#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 4044#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x141d 4045#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 4046#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x141e 4047#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 4048#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x141f 4049#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 4050#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x1420 4051#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 4052#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x1421 4053#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 4054#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x1422 4055#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 4056#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x1423 4057#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 4058#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x1424 4059#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 4060#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x1425 4061#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 4062#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x1426 4063#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 4064#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x1427 4065#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 4066#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x1428 4067#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 4068#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x1429 4069#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 4070#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x142a 4071#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 4072#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x142b 4073#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 4074#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x142c 4075#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 4076 4077 4078// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec 4079// base address: 0x208 4080#define mmMPCC_OGAM2_MPCC_OGAM_MODE 0x1430 4081#define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX 2 4082#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x1431 4083#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 4084#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x1432 4085#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 2 4086#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL 0x1433 4087#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 4088#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x1434 4089#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 4090#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x1435 4091#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 4092#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x1436 4093#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 4094#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1437 4095#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 4096#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1438 4097#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 4098#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x1439 4099#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 4100#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x143a 4101#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4102#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x143b 4103#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4104#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x143c 4105#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4106#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x143d 4107#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4108#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x143e 4109#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4110#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x143f 4111#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4112#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x1440 4113#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 4114#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x1441 4115#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 4116#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x1442 4117#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 4118#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x1443 4119#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 4120#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x1444 4121#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 4122#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x1445 4123#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 4124#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x1446 4125#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 4126#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x1447 4127#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 4128#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x1448 4129#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 4130#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x1449 4131#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 4132#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x144a 4133#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 4134#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x144b 4135#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 4136#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x144c 4137#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 4138#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x144d 4139#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 4140#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x144e 4141#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 4142#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x144f 4143#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 4144#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x1450 4145#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 4146#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x1451 4147#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 4148#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x1452 4149#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 4150#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x1453 4151#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 4152#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1454 4153#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 4154#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1455 4155#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 4156#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1456 4157#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 4158#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x1457 4159#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4160#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x1458 4161#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4162#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x1459 4163#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4164#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x145a 4165#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4166#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x145b 4167#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4168#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x145c 4169#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4170#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x145d 4171#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 4172#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x145e 4173#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 4174#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x145f 4175#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 4176#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x1460 4177#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 4178#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x1461 4179#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 4180#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x1462 4181#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 4182#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x1463 4183#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 4184#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x1464 4185#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 4186#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x1465 4187#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 4188#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x1466 4189#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 4190#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x1467 4191#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 4192#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x1468 4193#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 4194#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x1469 4195#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 4196#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x146a 4197#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 4198#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x146b 4199#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 4200#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x146c 4201#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 4202#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x146d 4203#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 4204 4205 4206// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec 4207// base address: 0x30c 4208#define mmMPCC_OGAM3_MPCC_OGAM_MODE 0x1471 4209#define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX 2 4210#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x1472 4211#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 4212#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x1473 4213#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 2 4214#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL 0x1474 4215#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 4216#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x1475 4217#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 4218#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x1476 4219#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 4220#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x1477 4221#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 4222#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1478 4223#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 4224#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1479 4225#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 4226#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x147a 4227#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 4228#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x147b 4229#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4230#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x147c 4231#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4232#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x147d 4233#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4234#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x147e 4235#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4236#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x147f 4237#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4238#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x1480 4239#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4240#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x1481 4241#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 4242#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x1482 4243#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 4244#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x1483 4245#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 4246#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x1484 4247#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 4248#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x1485 4249#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 4250#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x1486 4251#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 4252#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x1487 4253#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 4254#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x1488 4255#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 4256#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x1489 4257#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 4258#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x148a 4259#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 4260#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x148b 4261#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 4262#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x148c 4263#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 4264#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x148d 4265#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 4266#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x148e 4267#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 4268#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x148f 4269#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 4270#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x1490 4271#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 4272#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x1491 4273#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 4274#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x1492 4275#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 4276#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x1493 4277#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 4278#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x1494 4279#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 4280#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1495 4281#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 4282#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1496 4283#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 4284#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1497 4285#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 4286#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x1498 4287#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4288#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x1499 4289#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4290#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x149a 4291#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4292#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x149b 4293#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4294#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x149c 4295#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4296#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x149d 4297#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4298#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x149e 4299#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 4300#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x149f 4301#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 4302#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x14a0 4303#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 4304#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x14a1 4305#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 4306#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x14a2 4307#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 4308#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x14a3 4309#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 4310#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x14a4 4311#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 4312#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x14a5 4313#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 4314#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x14a6 4315#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 4316#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x14a7 4317#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 4318#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x14a8 4319#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 4320#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x14a9 4321#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 4322#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x14aa 4323#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 4324#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x14ab 4325#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 4326#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x14ac 4327#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 4328#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x14ad 4329#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 4330#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x14ae 4331#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 4332 4333 4334// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec 4335// base address: 0x410 4336#define mmMPCC_OGAM4_MPCC_OGAM_MODE 0x14b2 4337#define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX 2 4338#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x14b3 4339#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 4340#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x14b4 4341#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 2 4342#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL 0x14b5 4343#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 4344#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x14b6 4345#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 4346#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x14b7 4347#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 4348#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x14b8 4349#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 4350#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14b9 4351#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 4352#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14ba 4353#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 4354#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14bb 4355#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 4356#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x14bc 4357#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4358#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x14bd 4359#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4360#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x14be 4361#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4362#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x14bf 4363#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4364#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x14c0 4365#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4366#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x14c1 4367#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4368#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x14c2 4369#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 4370#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x14c3 4371#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 4372#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x14c4 4373#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 4374#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x14c5 4375#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 4376#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x14c6 4377#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 4378#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x14c7 4379#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 4380#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x14c8 4381#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 4382#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x14c9 4383#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 4384#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x14ca 4385#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 4386#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x14cb 4387#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 4388#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x14cc 4389#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 4390#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x14cd 4391#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 4392#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x14ce 4393#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 4394#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x14cf 4395#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 4396#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x14d0 4397#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 4398#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x14d1 4399#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 4400#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x14d2 4401#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 4402#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x14d3 4403#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 4404#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x14d4 4405#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 4406#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x14d5 4407#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 4408#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x14d6 4409#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 4410#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x14d7 4411#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 4412#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x14d8 4413#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 4414#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x14d9 4415#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4416#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x14da 4417#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4418#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x14db 4419#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4420#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x14dc 4421#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4422#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x14dd 4423#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4424#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x14de 4425#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4426#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x14df 4427#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 4428#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x14e0 4429#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 4430#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x14e1 4431#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 4432#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x14e2 4433#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 4434#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x14e3 4435#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 4436#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x14e4 4437#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 4438#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x14e5 4439#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 4440#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x14e6 4441#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 4442#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x14e7 4443#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 4444#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x14e8 4445#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 4446#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x14e9 4447#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 4448#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x14ea 4449#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 4450#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x14eb 4451#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 4452#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x14ec 4453#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 4454#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x14ed 4455#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 4456#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x14ee 4457#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 4458#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x14ef 4459#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 4460 4461 4462// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 4463// base address: 0x0 4464#define mmMPC_OUT_CSC_COEF_FORMAT 0x15b6 4465#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 2 4466#define mmMPC_OUT0_CSC_MODE 0x15b7 4467#define mmMPC_OUT0_CSC_MODE_BASE_IDX 2 4468#define mmMPC_OUT0_CSC_C11_C12_A 0x15b8 4469#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 2 4470#define mmMPC_OUT0_CSC_C13_C14_A 0x15b9 4471#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 2 4472#define mmMPC_OUT0_CSC_C21_C22_A 0x15ba 4473#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 2 4474#define mmMPC_OUT0_CSC_C23_C24_A 0x15bb 4475#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 2 4476#define mmMPC_OUT0_CSC_C31_C32_A 0x15bc 4477#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 2 4478#define mmMPC_OUT0_CSC_C33_C34_A 0x15bd 4479#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 2 4480#define mmMPC_OUT0_CSC_C11_C12_B 0x15be 4481#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 2 4482#define mmMPC_OUT0_CSC_C13_C14_B 0x15bf 4483#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 2 4484#define mmMPC_OUT0_CSC_C21_C22_B 0x15c0 4485#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 2 4486#define mmMPC_OUT0_CSC_C23_C24_B 0x15c1 4487#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 2 4488#define mmMPC_OUT0_CSC_C31_C32_B 0x15c2 4489#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 2 4490#define mmMPC_OUT0_CSC_C33_C34_B 0x15c3 4491#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 2 4492#define mmMPC_OUT1_CSC_MODE 0x15c4 4493#define mmMPC_OUT1_CSC_MODE_BASE_IDX 2 4494#define mmMPC_OUT1_CSC_C11_C12_A 0x15c5 4495#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 2 4496#define mmMPC_OUT1_CSC_C13_C14_A 0x15c6 4497#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 2 4498#define mmMPC_OUT1_CSC_C21_C22_A 0x15c7 4499#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 2 4500#define mmMPC_OUT1_CSC_C23_C24_A 0x15c8 4501#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 2 4502#define mmMPC_OUT1_CSC_C31_C32_A 0x15c9 4503#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 2 4504#define mmMPC_OUT1_CSC_C33_C34_A 0x15ca 4505#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 2 4506#define mmMPC_OUT1_CSC_C11_C12_B 0x15cb 4507#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 2 4508#define mmMPC_OUT1_CSC_C13_C14_B 0x15cc 4509#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 2 4510#define mmMPC_OUT1_CSC_C21_C22_B 0x15cd 4511#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 2 4512#define mmMPC_OUT1_CSC_C23_C24_B 0x15ce 4513#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 2 4514#define mmMPC_OUT1_CSC_C31_C32_B 0x15cf 4515#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 2 4516#define mmMPC_OUT1_CSC_C33_C34_B 0x15d0 4517#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 2 4518 4519 4520// addressBlock: dce_dc_opp_fmt0_dispdec 4521// base address: 0x0 4522#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c 4523#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 4524#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d 4525#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 4526#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e 4527#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 4528#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 4529#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 4530#define mmFMT0_FMT_CONTROL 0x1840 4531#define mmFMT0_FMT_CONTROL_BASE_IDX 2 4532#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 4533#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 4534#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842 4535#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 4536#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843 4537#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 4538#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844 4539#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 4540#define mmFMT0_FMT_CLAMP_CNTL 0x1845 4541#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 4542#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 4543#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 4544#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 4545#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 4546#define mmFMT0_FMT_422_CONTROL 0x1849 4547#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2 4548 4549 4550// addressBlock: dce_dc_opp_dpg0_dispdec 4551// base address: 0x0 4552#define mmDPG0_DPG_CONTROL 0x1854 4553#define mmDPG0_DPG_CONTROL_BASE_IDX 2 4554#define mmDPG0_DPG_RAMP_CONTROL 0x1855 4555#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 4556#define mmDPG0_DPG_DIMENSIONS 0x1856 4557#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2 4558#define mmDPG0_DPG_COLOUR_R_CR 0x1857 4559#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 4560#define mmDPG0_DPG_COLOUR_G_Y 0x1858 4561#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 4562#define mmDPG0_DPG_COLOUR_B_CB 0x1859 4563#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 4564#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a 4565#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 4566#define mmDPG0_DPG_STATUS 0x185b 4567#define mmDPG0_DPG_STATUS_BASE_IDX 2 4568 4569 4570// addressBlock: dce_dc_opp_oppbuf0_dispdec 4571// base address: 0x0 4572#define mmOPPBUF0_OPPBUF_CONTROL 0x1884 4573#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 4574#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 4575#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 4576#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 4577#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 4578 4579 4580// addressBlock: dce_dc_opp_opp_pipe0_dispdec 4581// base address: 0x0 4582#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 4583#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 4584 4585 4586// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 4587// base address: 0x0 4588#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 4589#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 4590#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 4591#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 4592#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 4593#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 4594#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 4595#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 4596#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 4597#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 4598 4599 4600// addressBlock: dce_dc_opp_fmt1_dispdec 4601// base address: 0x168 4602#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896 4603#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 4604#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897 4605#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 4606#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898 4607#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 4608#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 4609#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 4610#define mmFMT1_FMT_CONTROL 0x189a 4611#define mmFMT1_FMT_CONTROL_BASE_IDX 2 4612#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 4613#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 4614#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c 4615#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 4616#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d 4617#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 4618#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e 4619#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 4620#define mmFMT1_FMT_CLAMP_CNTL 0x189f 4621#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 4622#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 4623#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 4624#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 4625#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 4626#define mmFMT1_FMT_422_CONTROL 0x18a3 4627#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2 4628 4629 4630// addressBlock: dce_dc_opp_dpg1_dispdec 4631// base address: 0x168 4632#define mmDPG1_DPG_CONTROL 0x18ae 4633#define mmDPG1_DPG_CONTROL_BASE_IDX 2 4634#define mmDPG1_DPG_RAMP_CONTROL 0x18af 4635#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 4636#define mmDPG1_DPG_DIMENSIONS 0x18b0 4637#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2 4638#define mmDPG1_DPG_COLOUR_R_CR 0x18b1 4639#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 4640#define mmDPG1_DPG_COLOUR_G_Y 0x18b2 4641#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 4642#define mmDPG1_DPG_COLOUR_B_CB 0x18b3 4643#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 4644#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4 4645#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 4646#define mmDPG1_DPG_STATUS 0x18b5 4647#define mmDPG1_DPG_STATUS_BASE_IDX 2 4648 4649 4650// addressBlock: dce_dc_opp_oppbuf1_dispdec 4651// base address: 0x168 4652#define mmOPPBUF1_OPPBUF_CONTROL 0x18de 4653#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 4654#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 4655#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 4656#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 4657#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 4658 4659 4660// addressBlock: dce_dc_opp_opp_pipe1_dispdec 4661// base address: 0x168 4662#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 4663#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 4664 4665// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 4666// base address: 0x168 4667#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 4668#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 4669#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 4670#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 4671#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 4672#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 4673#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 4674#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 4675#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 4676#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 4677 4678 4679// addressBlock: dce_dc_opp_opp_top_dispdec 4680// base address: 0x0 4681#define mmOPP_TOP_CLK_CONTROL 0x1a5e 4682#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2 4683 4684 4685// addressBlock: dce_dc_optc_odm0_dispdec 4686// base address: 0x0 4687#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 4688#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 4689#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 4690#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 4691#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 4692#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 4693#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd 4694#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 4695#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace 4696#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 4697#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 4698#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 4699 4700// addressBlock: dce_dc_optc_odm1_dispdec 4701// base address: 0x40 4702#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 4703#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 4704#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 4705#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 4706#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 4707#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 4708#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add 4709#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 4710#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade 4711#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 4712#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 4713#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 4714 4715 4716// addressBlock: dce_dc_optc_otg0_dispdec 4717// base address: 0x0 4718#define mmOTG0_OTG_H_TOTAL 0x1b2a 4719#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2 4720#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b 4721#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 4722#define mmOTG0_OTG_H_SYNC_A 0x1b2c 4723#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2 4724#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 4725#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 4726#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e 4727#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 4728#define mmOTG0_OTG_V_TOTAL 0x1b2f 4729#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2 4730#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30 4731#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 4732#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31 4733#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 4734#define mmOTG0_OTG_V_TOTAL_MID 0x1b32 4735#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 4736#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33 4737#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 4738#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 4739#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 4740#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 4741#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 4742#define mmOTG0_OTG_V_BLANK_START_END 0x1b36 4743#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 4744#define mmOTG0_OTG_V_SYNC_A 0x1b37 4745#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2 4746#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38 4747#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 4748#define mmOTG0_OTG_TRIGA_CNTL 0x1b39 4749#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 4750#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 4751#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 4752#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b 4753#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 4754#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 4755#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 4756#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 4757#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 4758#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 4759#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 4760#define mmOTG0_OTG_CONTROL 0x1b41 4761#define mmOTG0_OTG_CONTROL_BASE_IDX 2 4762#define mmOTG0_OTG_BLANK_CONTROL 0x1b42 4763#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2 4764#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44 4765#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 4766#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45 4767#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 4768#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 4769#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 4770#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 4771#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 4772#define mmOTG0_OTG_STATUS 0x1b49 4773#define mmOTG0_OTG_STATUS_BASE_IDX 2 4774#define mmOTG0_OTG_STATUS_POSITION 0x1b4a 4775#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2 4776#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b 4777#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 4778#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 4779#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 4780#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d 4781#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 4782#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e 4783#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 4784#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f 4785#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 4786#define mmOTG0_OTG_COUNT_RESET 0x1b50 4787#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2 4788#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 4789#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 4790#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 4791#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 4792#define mmOTG0_OTG_STEREO_STATUS 0x1b53 4793#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2 4794#define mmOTG0_OTG_STEREO_CONTROL 0x1b54 4795#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 4796#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55 4797#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 4798#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 4799#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 4800#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57 4801#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 4802#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58 4803#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 4804#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59 4805#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 4806#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a 4807#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 4808#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 4809#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 4810#define mmOTG0_OTG_MASTER_EN 0x1b5c 4811#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2 4812#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e 4813#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2 4814#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f 4815#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 4816#define mmOTG0_OTG_BLACK_COLOR 0x1b60 4817#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2 4818#define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b61 4819#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2 4820#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 4821#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 4822#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 4823#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 4824#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 4825#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 4826#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 4827#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 4828#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 4829#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 4830#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 4831#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 4832#define mmOTG0_OTG_CRC_CNTL 0x1b68 4833#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2 4834#define mmOTG0_OTG_CRC_CNTL2 0x1b69 4835#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2 4836#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a 4837#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 4838#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b 4839#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 4840#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c 4841#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 4842#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d 4843#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 4844#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e 4845#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 4846#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f 4847#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 4848#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 4849#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 4850#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 4851#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 4852#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 4853#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 4854#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 4855#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 4856#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74 4857#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 4858#define mmOTG0_OTG_CRC1_DATA_B 0x1b75 4859#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 4860#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a 4861#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 4862#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b 4863#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 4864#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 4865#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 4866#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 4867#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 4868#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84 4869#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 4870#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 4871#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 4872#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86 4873#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 4874#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87 4875#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 4876#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88 4877#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 4878#define mmOTG0_OTG_VREADY_PARAM 0x1b89 4879#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2 4880#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a 4881#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 4882#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b 4883#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 4884#define mmOTG0_OTG_GSL_CONTROL 0x1b8c 4885#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2 4886#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d 4887#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 4888#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e 4889#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 4890#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f 4891#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 4892#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90 4893#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 4894#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91 4895#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 4896#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92 4897#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 4898#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93 4899#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 4900#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94 4901#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 4902#define mmOTG0_OTG_DRR_CONTROL 0x1b97 4903#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2 4904#define mmOTG0_OTG_DSC_START_POSITION 0x1b99 4905#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 4906 4907// addressBlock: dce_dc_optc_otg1_dispdec 4908// base address: 0x200 4909#define mmOTG1_OTG_H_TOTAL 0x1baa 4910#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2 4911#define mmOTG1_OTG_H_BLANK_START_END 0x1bab 4912#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 4913#define mmOTG1_OTG_H_SYNC_A 0x1bac 4914#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2 4915#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad 4916#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 4917#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae 4918#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 4919#define mmOTG1_OTG_V_TOTAL 0x1baf 4920#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2 4921#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0 4922#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 4923#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1 4924#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 4925#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2 4926#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 4927#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 4928#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 4929#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 4930#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 4931#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 4932#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 4933#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6 4934#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 4935#define mmOTG1_OTG_V_SYNC_A 0x1bb7 4936#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2 4937#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 4938#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 4939#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9 4940#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 4941#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 4942#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 4943#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb 4944#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 4945#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 4946#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 4947#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 4948#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 4949#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 4950#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 4951#define mmOTG1_OTG_CONTROL 0x1bc1 4952#define mmOTG1_OTG_CONTROL_BASE_IDX 2 4953#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2 4954#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2 4955#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 4956#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 4957#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 4958#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 4959#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 4960#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 4961#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 4962#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 4963#define mmOTG1_OTG_STATUS 0x1bc9 4964#define mmOTG1_OTG_STATUS_BASE_IDX 2 4965#define mmOTG1_OTG_STATUS_POSITION 0x1bca 4966#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2 4967#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb 4968#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 4969#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 4970#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 4971#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd 4972#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 4973#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce 4974#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 4975#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf 4976#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 4977#define mmOTG1_OTG_COUNT_RESET 0x1bd0 4978#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2 4979#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 4980#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 4981#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 4982#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 4983#define mmOTG1_OTG_STEREO_STATUS 0x1bd3 4984#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2 4985#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4 4986#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 4987#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 4988#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 4989#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 4990#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 4991#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 4992#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 4993#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 4994#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 4995#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 4996#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 4997#define mmOTG1_OTG_UPDATE_LOCK 0x1bda 4998#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 4999#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 5000#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 5001#define mmOTG1_OTG_MASTER_EN 0x1bdc 5002#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2 5003#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde 5004#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2 5005#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf 5006#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 5007#define mmOTG1_OTG_BLACK_COLOR 0x1be0 5008#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2 5009#define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be1 5010#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2 5011#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 5012#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 5013#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 5014#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 5015#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 5016#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 5017#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 5018#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 5019#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 5020#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 5021#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 5022#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 5023#define mmOTG1_OTG_CRC_CNTL 0x1be8 5024#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2 5025#define mmOTG1_OTG_CRC_CNTL2 0x1be9 5026#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2 5027#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea 5028#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 5029#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb 5030#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 5031#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec 5032#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 5033#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed 5034#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 5035#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee 5036#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 5037#define mmOTG1_OTG_CRC0_DATA_B 0x1bef 5038#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 5039#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 5040#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 5041#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 5042#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 5043#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 5044#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 5045#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 5046#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 5047#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4 5048#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 5049#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5 5050#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 5051#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa 5052#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 5053#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb 5054#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 5055#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 5056#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 5057#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 5058#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 5059#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04 5060#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 5061#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 5062#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 5063#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06 5064#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 5065#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07 5066#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 5067#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08 5068#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 5069#define mmOTG1_OTG_VREADY_PARAM 0x1c09 5070#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2 5071#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a 5072#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 5073#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b 5074#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 5075#define mmOTG1_OTG_GSL_CONTROL 0x1c0c 5076#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2 5077#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d 5078#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 5079#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e 5080#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 5081#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f 5082#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 5083#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10 5084#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 5085#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11 5086#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 5087#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12 5088#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 5089#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13 5090#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 5091#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14 5092#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 5093#define mmOTG1_OTG_DRR_CONTROL 0x1c17 5094#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2 5095#define mmOTG1_OTG_DSC_START_POSITION 0x1c19 5096#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 5097 5098 5099// addressBlock: dce_dc_optc_optc_misc_dispdec 5100// base address: 0x0 5101#define mmDWB_SOURCE_SELECT 0x1e2a 5102#define mmDWB_SOURCE_SELECT_BASE_IDX 2 5103#define mmGSL_SOURCE_SELECT 0x1e2b 5104#define mmGSL_SOURCE_SELECT_BASE_IDX 2 5105#define mmOPTC_CLOCK_CONTROL 0x1e2c 5106#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2 5107 5108 5109// addressBlock: dce_dc_dio_dout_i2c_dispdec 5110// base address: 0x0 5111#define mmDC_I2C_CONTROL 0x1e98 5112#define mmDC_I2C_CONTROL_BASE_IDX 2 5113#define mmDC_I2C_ARBITRATION 0x1e99 5114#define mmDC_I2C_ARBITRATION_BASE_IDX 2 5115#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a 5116#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 5117#define mmDC_I2C_SW_STATUS 0x1e9b 5118#define mmDC_I2C_SW_STATUS_BASE_IDX 2 5119#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c 5120#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 5121#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d 5122#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 5123#define mmDC_I2C_DDC1_SPEED 0x1ea2 5124#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2 5125#define mmDC_I2C_DDC1_SETUP 0x1ea3 5126#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2 5127#define mmDC_I2C_DDC2_SPEED 0x1ea4 5128#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2 5129#define mmDC_I2C_DDC2_SETUP 0x1ea5 5130#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2 5131#define mmDC_I2C_TRANSACTION0 0x1eae 5132#define mmDC_I2C_TRANSACTION0_BASE_IDX 2 5133#define mmDC_I2C_TRANSACTION1 0x1eaf 5134#define mmDC_I2C_TRANSACTION1_BASE_IDX 2 5135#define mmDC_I2C_TRANSACTION2 0x1eb0 5136#define mmDC_I2C_TRANSACTION2_BASE_IDX 2 5137#define mmDC_I2C_TRANSACTION3 0x1eb1 5138#define mmDC_I2C_TRANSACTION3_BASE_IDX 2 5139#define mmDC_I2C_DATA 0x1eb2 5140#define mmDC_I2C_DATA_BASE_IDX 2 5141#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6 5142#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 5143#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 5144#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 5145 5146 5147// addressBlock: dce_dc_dio_dio_misc_dispdec 5148// base address: 0x0 5149#define mmDIO_SCRATCH0 0x1eca 5150#define mmDIO_SCRATCH0_BASE_IDX 2 5151#define mmDIO_SCRATCH1 0x1ecb 5152#define mmDIO_SCRATCH1_BASE_IDX 2 5153#define mmDIO_SCRATCH2 0x1ecc 5154#define mmDIO_SCRATCH2_BASE_IDX 2 5155#define mmDIO_SCRATCH3 0x1ecd 5156#define mmDIO_SCRATCH3_BASE_IDX 2 5157#define mmDIO_SCRATCH4 0x1ece 5158#define mmDIO_SCRATCH4_BASE_IDX 2 5159#define mmDIO_SCRATCH5 0x1ecf 5160#define mmDIO_SCRATCH5_BASE_IDX 2 5161#define mmDIO_SCRATCH6 0x1ed0 5162#define mmDIO_SCRATCH6_BASE_IDX 2 5163#define mmDIO_SCRATCH7 0x1ed1 5164#define mmDIO_SCRATCH7_BASE_IDX 2 5165#define mmDIO_MEM_PWR_STATUS 0x1edd 5166#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2 5167#define mmDIO_MEM_PWR_CTRL 0x1ede 5168#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2 5169#define mmDIO_MEM_PWR_CTRL2 0x1edf 5170#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2 5171#define mmDIO_CLK_CNTL 0x1ee0 5172#define mmDIO_CLK_CNTL_BASE_IDX 2 5173#define mmDIO_MEM_PWR_CTRL3 0x1ee1 5174#define mmDIO_MEM_PWR_CTRL3_BASE_IDX 2 5175#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4 5176#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 5177#define mmDIG_SOFT_RESET 0x1eee 5178#define mmDIG_SOFT_RESET_BASE_IDX 2 5179#define mmDIO_MEM_PWR_STATUS1 0x1ef0 5180#define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2 5181#define mmDIO_CLK_CNTL2 0x1ef2 5182#define mmDIO_CLK_CNTL2_BASE_IDX 2 5183#define mmDIO_CLK_CNTL3 0x1ef3 5184#define mmDIO_CLK_CNTL3_BASE_IDX 2 5185#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 5186#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 5187#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 5188#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 5189#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 5190#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 5191 5192 5193// addressBlock: dce_dc_dio_hpd0_dispdec 5194// base address: 0x0 5195#define mmHPD0_DC_HPD_INT_STATUS 0x1f14 5196#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 5197#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15 5198#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 5199#define mmHPD0_DC_HPD_CONTROL 0x1f16 5200#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 5201#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 5202#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 5203#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 5204#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 5205 5206 5207// addressBlock: dce_dc_dio_hpd1_dispdec 5208// base address: 0x20 5209#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c 5210#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 5211#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d 5212#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 5213#define mmHPD1_DC_HPD_CONTROL 0x1f1e 5214#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 5215#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 5216#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 5217#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 5218#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 5219 5220// addressBlock: dce_dc_dio_dp_aux0_dispdec 5221// base address: 0x0 5222#define mmDP_AUX0_AUX_CONTROL 0x1f50 5223#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 5224#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51 5225#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 5226#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52 5227#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 5228#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 5229#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 5230#define mmDP_AUX0_AUX_SW_STATUS 0x1f54 5231#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 5232#define mmDP_AUX0_AUX_LS_STATUS 0x1f55 5233#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 5234#define mmDP_AUX0_AUX_SW_DATA 0x1f56 5235#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 5236#define mmDP_AUX0_AUX_LS_DATA 0x1f57 5237#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 5238#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 5239#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 5240#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 5241#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 5242#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 5243#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 5244#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 5245#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 5246#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 5247#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 5248#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 5249#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 5250 5251 5252// addressBlock: dce_dc_dio_dp_aux1_dispdec 5253// base address: 0x70 5254#define mmDP_AUX1_AUX_CONTROL 0x1f6c 5255#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 5256#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d 5257#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 5258#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e 5259#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 5260#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 5261#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 5262#define mmDP_AUX1_AUX_SW_STATUS 0x1f70 5263#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 5264#define mmDP_AUX1_AUX_LS_STATUS 0x1f71 5265#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 5266#define mmDP_AUX1_AUX_SW_DATA 0x1f72 5267#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 5268#define mmDP_AUX1_AUX_LS_DATA 0x1f73 5269#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 5270#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 5271#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 5272#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 5273#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 5274#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 5275#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 5276#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 5277#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 5278#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 5279#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 5280#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 5281#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 5282 5283 5284// addressBlock: dce_dc_dio_dig0_dispdec 5285// base address: 0x0 5286#define mmDIG0_DIG_FE_CNTL 0x2068 5287#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2 5288#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069 5289#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 5290#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a 5291#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 5292#define mmDIG0_DIG_CLOCK_PATTERN 0x206b 5293#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 5294#define mmDIG0_DIG_TEST_PATTERN 0x206c 5295#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 5296#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d 5297#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 5298#define mmDIG0_DIG_FIFO_STATUS 0x206e 5299#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 5300#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x206f 5301#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 5302#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x2070 5303#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 5304#define mmDIG0_HDMI_CONTROL 0x2071 5305#define mmDIG0_HDMI_CONTROL_BASE_IDX 2 5306#define mmDIG0_HDMI_STATUS 0x2072 5307#define mmDIG0_HDMI_STATUS_BASE_IDX 2 5308#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073 5309#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 5310#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074 5311#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 5312#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075 5313#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 5314#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076 5315#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 5316#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077 5317#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 5318#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078 5319#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 5320#define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079 5321#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 5322#define mmDIG0_HDMI_GC 0x207b 5323#define mmDIG0_HDMI_GC_BASE_IDX 2 5324#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c 5325#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 5326#define mmDIG0_AFMT_ISRC1_0 0x207d 5327#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2 5328#define mmDIG0_AFMT_ISRC1_1 0x207e 5329#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2 5330#define mmDIG0_AFMT_ISRC1_2 0x207f 5331#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2 5332#define mmDIG0_AFMT_ISRC1_3 0x2080 5333#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2 5334#define mmDIG0_AFMT_ISRC1_4 0x2081 5335#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2 5336#define mmDIG0_AFMT_ISRC2_0 0x2082 5337#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2 5338#define mmDIG0_AFMT_ISRC2_1 0x2083 5339#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2 5340#define mmDIG0_AFMT_ISRC2_2 0x2084 5341#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2 5342#define mmDIG0_AFMT_ISRC2_3 0x2085 5343#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2 5344#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086 5345#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 5346#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087 5347#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 5348#define mmDIG0_HDMI_DB_CONTROL 0x2088 5349#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2 5350#define mmDIG0_DME_CONTROL 0x2089 5351#define mmDIG0_DME_CONTROL_BASE_IDX 2 5352#define mmDIG0_AFMT_MPEG_INFO0 0x208a 5353#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2 5354#define mmDIG0_AFMT_MPEG_INFO1 0x208b 5355#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2 5356#define mmDIG0_AFMT_GENERIC_HDR 0x208c 5357#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2 5358#define mmDIG0_AFMT_GENERIC_0 0x208d 5359#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2 5360#define mmDIG0_AFMT_GENERIC_1 0x208e 5361#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2 5362#define mmDIG0_AFMT_GENERIC_2 0x208f 5363#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2 5364#define mmDIG0_AFMT_GENERIC_3 0x2090 5365#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2 5366#define mmDIG0_AFMT_GENERIC_4 0x2091 5367#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2 5368#define mmDIG0_AFMT_GENERIC_5 0x2092 5369#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2 5370#define mmDIG0_AFMT_GENERIC_6 0x2093 5371#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2 5372#define mmDIG0_AFMT_GENERIC_7 0x2094 5373#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2 5374#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095 5375#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 5376#define mmDIG0_HDMI_ACR_32_0 0x2096 5377#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 5378#define mmDIG0_HDMI_ACR_32_1 0x2097 5379#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 5380#define mmDIG0_HDMI_ACR_44_0 0x2098 5381#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 5382#define mmDIG0_HDMI_ACR_44_1 0x2099 5383#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 5384#define mmDIG0_HDMI_ACR_48_0 0x209a 5385#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 5386#define mmDIG0_HDMI_ACR_48_1 0x209b 5387#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 5388#define mmDIG0_HDMI_ACR_STATUS_0 0x209c 5389#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 5390#define mmDIG0_HDMI_ACR_STATUS_1 0x209d 5391#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 5392#define mmDIG0_AFMT_AUDIO_INFO0 0x209e 5393#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2 5394#define mmDIG0_AFMT_AUDIO_INFO1 0x209f 5395#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2 5396#define mmDIG0_AFMT_60958_0 0x20a0 5397#define mmDIG0_AFMT_60958_0_BASE_IDX 2 5398#define mmDIG0_AFMT_60958_1 0x20a1 5399#define mmDIG0_AFMT_60958_1_BASE_IDX 2 5400#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2 5401#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 5402#define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3 5403#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2 5404#define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4 5405#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2 5406#define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5 5407#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2 5408#define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6 5409#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2 5410#define mmDIG0_AFMT_60958_2 0x20a7 5411#define mmDIG0_AFMT_60958_2_BASE_IDX 2 5412#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8 5413#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 5414#define mmDIG0_AFMT_STATUS 0x20a9 5415#define mmDIG0_AFMT_STATUS_BASE_IDX 2 5416#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa 5417#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 5418#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab 5419#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 5420#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac 5421#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 5422#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad 5423#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 5424#define mmDIG0_DIG_BE_CNTL 0x20af 5425#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2 5426#define mmDIG0_DIG_BE_EN_CNTL 0x20b0 5427#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 5428#define mmDIG0_TMDS_CNTL 0x20d3 5429#define mmDIG0_TMDS_CNTL_BASE_IDX 2 5430#define mmDIG0_TMDS_CONTROL_CHAR 0x20d4 5431#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 5432#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5 5433#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 5434#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6 5435#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 5436#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7 5437#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 5438#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8 5439#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 5440#define mmDIG0_TMDS_CTL_BITS 0x20da 5441#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 5442#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db 5443#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 5444#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20dc 5445#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 5446#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd 5447#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 5448#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de 5449#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 5450#define mmDIG0_DIG_VERSION 0x20e0 5451#define mmDIG0_DIG_VERSION_BASE_IDX 2 5452#define mmDIG0_DIG_LANE_ENABLE 0x20e1 5453#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 5454#define mmDIG0_AFMT_CNTL 0x20e6 5455#define mmDIG0_AFMT_CNTL_BASE_IDX 2 5456#define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7 5457#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 5458#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20f6 5459#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 5460 5461 5462// addressBlock: dce_dc_dio_dp0_dispdec 5463// base address: 0x0 5464#define mmDP0_DP_LINK_CNTL 0x2108 5465#define mmDP0_DP_LINK_CNTL_BASE_IDX 2 5466#define mmDP0_DP_PIXEL_FORMAT 0x2109 5467#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 5468#define mmDP0_DP_MSA_COLORIMETRY 0x210a 5469#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 5470#define mmDP0_DP_CONFIG 0x210b 5471#define mmDP0_DP_CONFIG_BASE_IDX 2 5472#define mmDP0_DP_VID_STREAM_CNTL 0x210c 5473#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 5474#define mmDP0_DP_STEER_FIFO 0x210d 5475#define mmDP0_DP_STEER_FIFO_BASE_IDX 2 5476#define mmDP0_DP_MSA_MISC 0x210e 5477#define mmDP0_DP_MSA_MISC_BASE_IDX 2 5478#define mmDP0_DP_VID_TIMING 0x2110 5479#define mmDP0_DP_VID_TIMING_BASE_IDX 2 5480#define mmDP0_DP_VID_N 0x2111 5481#define mmDP0_DP_VID_N_BASE_IDX 2 5482#define mmDP0_DP_VID_M 0x2112 5483#define mmDP0_DP_VID_M_BASE_IDX 2 5484#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113 5485#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 5486#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114 5487#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 5488#define mmDP0_DP_VID_MSA_VBID 0x2115 5489#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 5490#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116 5491#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 5492#define mmDP0_DP_DPHY_CNTL 0x2117 5493#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2 5494#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 5495#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 5496#define mmDP0_DP_DPHY_SYM0 0x2119 5497#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2 5498#define mmDP0_DP_DPHY_SYM1 0x211a 5499#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2 5500#define mmDP0_DP_DPHY_SYM2 0x211b 5501#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2 5502#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c 5503#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 5504#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d 5505#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 5506#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e 5507#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 5508#define mmDP0_DP_DPHY_CRC_EN 0x211f 5509#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 5510#define mmDP0_DP_DPHY_CRC_CNTL 0x2120 5511#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 5512#define mmDP0_DP_DPHY_CRC_RESULT 0x2121 5513#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 5514#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122 5515#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 5516#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123 5517#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 5518#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124 5519#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 5520#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 5521#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 5522#define mmDP0_DP_SEC_CNTL 0x212b 5523#define mmDP0_DP_SEC_CNTL_BASE_IDX 2 5524#define mmDP0_DP_SEC_CNTL1 0x212c 5525#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2 5526#define mmDP0_DP_SEC_FRAMING1 0x212d 5527#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 5528#define mmDP0_DP_SEC_FRAMING2 0x212e 5529#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 5530#define mmDP0_DP_SEC_FRAMING3 0x212f 5531#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 5532#define mmDP0_DP_SEC_FRAMING4 0x2130 5533#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 5534#define mmDP0_DP_SEC_AUD_N 0x2131 5535#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2 5536#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132 5537#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 5538#define mmDP0_DP_SEC_AUD_M 0x2133 5539#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2 5540#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134 5541#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 5542#define mmDP0_DP_SEC_TIMESTAMP 0x2135 5543#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 5544#define mmDP0_DP_SEC_PACKET_CNTL 0x2136 5545#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 5546#define mmDP0_DP_MSE_RATE_CNTL 0x2137 5547#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 5548#define mmDP0_DP_MSE_RATE_UPDATE 0x2139 5549#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 5550#define mmDP0_DP_MSE_SAT0 0x213a 5551#define mmDP0_DP_MSE_SAT0_BASE_IDX 2 5552#define mmDP0_DP_MSE_SAT1 0x213b 5553#define mmDP0_DP_MSE_SAT1_BASE_IDX 2 5554#define mmDP0_DP_MSE_SAT2 0x213c 5555#define mmDP0_DP_MSE_SAT2_BASE_IDX 2 5556#define mmDP0_DP_MSE_SAT_UPDATE 0x213d 5557#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 5558#define mmDP0_DP_MSE_LINK_TIMING 0x213e 5559#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 5560#define mmDP0_DP_MSE_MISC_CNTL 0x213f 5561#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 5562#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 5563#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 5564#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 5565#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 5566#define mmDP0_DP_MSE_SAT0_STATUS 0x2147 5567#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 5568#define mmDP0_DP_MSE_SAT1_STATUS 0x2148 5569#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 5570#define mmDP0_DP_MSE_SAT2_STATUS 0x2149 5571#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 5572#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c 5573#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 5574#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d 5575#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 5576#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e 5577#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 5578#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f 5579#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 5580#define mmDP0_DP_DSC_CNTL 0x2152 5581#define mmDP0_DP_DSC_CNTL_BASE_IDX 2 5582#define mmDP0_DP_SEC_CNTL2 0x2153 5583#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2 5584#define mmDP0_DP_SEC_CNTL3 0x2154 5585#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2 5586#define mmDP0_DP_SEC_CNTL4 0x2155 5587#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2 5588#define mmDP0_DP_SEC_CNTL5 0x2156 5589#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2 5590#define mmDP0_DP_SEC_CNTL6 0x2157 5591#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2 5592#define mmDP0_DP_SEC_CNTL7 0x2158 5593#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2 5594#define mmDP0_DP_DB_CNTL 0x2159 5595#define mmDP0_DP_DB_CNTL_BASE_IDX 2 5596#define mmDP0_DP_MSA_VBID_MISC 0x215a 5597#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2 5598#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b 5599#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 5600#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c 5601#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 5602 5603 5604// addressBlock: dce_dc_dio_dig1_dispdec 5605// base address: 0x400 5606#define mmDIG1_DIG_FE_CNTL 0x2168 5607#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2 5608#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169 5609#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 5610#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a 5611#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 5612#define mmDIG1_DIG_CLOCK_PATTERN 0x216b 5613#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 5614#define mmDIG1_DIG_TEST_PATTERN 0x216c 5615#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 5616#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d 5617#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 5618#define mmDIG1_DIG_FIFO_STATUS 0x216e 5619#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 5620#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x216f 5621#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 5622#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x2170 5623#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 5624#define mmDIG1_HDMI_CONTROL 0x2171 5625#define mmDIG1_HDMI_CONTROL_BASE_IDX 2 5626#define mmDIG1_HDMI_STATUS 0x2172 5627#define mmDIG1_HDMI_STATUS_BASE_IDX 2 5628#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173 5629#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 5630#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174 5631#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 5632#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175 5633#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 5634#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176 5635#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 5636#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177 5637#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 5638#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178 5639#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 5640#define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179 5641#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 5642#define mmDIG1_HDMI_GC 0x217b 5643#define mmDIG1_HDMI_GC_BASE_IDX 2 5644#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c 5645#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 5646#define mmDIG1_AFMT_ISRC1_0 0x217d 5647#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2 5648#define mmDIG1_AFMT_ISRC1_1 0x217e 5649#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2 5650#define mmDIG1_AFMT_ISRC1_2 0x217f 5651#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2 5652#define mmDIG1_AFMT_ISRC1_3 0x2180 5653#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2 5654#define mmDIG1_AFMT_ISRC1_4 0x2181 5655#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2 5656#define mmDIG1_AFMT_ISRC2_0 0x2182 5657#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2 5658#define mmDIG1_AFMT_ISRC2_1 0x2183 5659#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2 5660#define mmDIG1_AFMT_ISRC2_2 0x2184 5661#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2 5662#define mmDIG1_AFMT_ISRC2_3 0x2185 5663#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2 5664#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186 5665#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 5666#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187 5667#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 5668#define mmDIG1_HDMI_DB_CONTROL 0x2188 5669#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2 5670#define mmDIG1_DME_CONTROL 0x2189 5671#define mmDIG1_DME_CONTROL_BASE_IDX 2 5672#define mmDIG1_AFMT_MPEG_INFO0 0x218a 5673#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2 5674#define mmDIG1_AFMT_MPEG_INFO1 0x218b 5675#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2 5676#define mmDIG1_AFMT_GENERIC_HDR 0x218c 5677#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2 5678#define mmDIG1_AFMT_GENERIC_0 0x218d 5679#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2 5680#define mmDIG1_AFMT_GENERIC_1 0x218e 5681#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2 5682#define mmDIG1_AFMT_GENERIC_2 0x218f 5683#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2 5684#define mmDIG1_AFMT_GENERIC_3 0x2190 5685#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2 5686#define mmDIG1_AFMT_GENERIC_4 0x2191 5687#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2 5688#define mmDIG1_AFMT_GENERIC_5 0x2192 5689#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2 5690#define mmDIG1_AFMT_GENERIC_6 0x2193 5691#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2 5692#define mmDIG1_AFMT_GENERIC_7 0x2194 5693#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2 5694#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195 5695#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 5696#define mmDIG1_HDMI_ACR_32_0 0x2196 5697#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 5698#define mmDIG1_HDMI_ACR_32_1 0x2197 5699#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 5700#define mmDIG1_HDMI_ACR_44_0 0x2198 5701#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 5702#define mmDIG1_HDMI_ACR_44_1 0x2199 5703#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 5704#define mmDIG1_HDMI_ACR_48_0 0x219a 5705#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 5706#define mmDIG1_HDMI_ACR_48_1 0x219b 5707#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 5708#define mmDIG1_HDMI_ACR_STATUS_0 0x219c 5709#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 5710#define mmDIG1_HDMI_ACR_STATUS_1 0x219d 5711#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 5712#define mmDIG1_AFMT_AUDIO_INFO0 0x219e 5713#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2 5714#define mmDIG1_AFMT_AUDIO_INFO1 0x219f 5715#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2 5716#define mmDIG1_AFMT_60958_0 0x21a0 5717#define mmDIG1_AFMT_60958_0_BASE_IDX 2 5718#define mmDIG1_AFMT_60958_1 0x21a1 5719#define mmDIG1_AFMT_60958_1_BASE_IDX 2 5720#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2 5721#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 5722#define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3 5723#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2 5724#define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4 5725#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2 5726#define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5 5727#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2 5728#define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6 5729#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2 5730#define mmDIG1_AFMT_60958_2 0x21a7 5731#define mmDIG1_AFMT_60958_2_BASE_IDX 2 5732#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8 5733#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 5734#define mmDIG1_AFMT_STATUS 0x21a9 5735#define mmDIG1_AFMT_STATUS_BASE_IDX 2 5736#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa 5737#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 5738#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab 5739#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 5740#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac 5741#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 5742#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad 5743#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 5744#define mmDIG1_DIG_BE_CNTL 0x21af 5745#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2 5746#define mmDIG1_DIG_BE_EN_CNTL 0x21b0 5747#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 5748#define mmDIG1_TMDS_CNTL 0x21d3 5749#define mmDIG1_TMDS_CNTL_BASE_IDX 2 5750#define mmDIG1_TMDS_CONTROL_CHAR 0x21d4 5751#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 5752#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5 5753#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 5754#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6 5755#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 5756#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7 5757#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 5758#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8 5759#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 5760#define mmDIG1_TMDS_CTL_BITS 0x21da 5761#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 5762#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db 5763#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 5764#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21dc 5765#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 5766#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd 5767#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 5768#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de 5769#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 5770#define mmDIG1_DIG_VERSION 0x21e0 5771#define mmDIG1_DIG_VERSION_BASE_IDX 2 5772#define mmDIG1_DIG_LANE_ENABLE 0x21e1 5773#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 5774#define mmDIG1_AFMT_CNTL 0x21e6 5775#define mmDIG1_AFMT_CNTL_BASE_IDX 2 5776#define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7 5777#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 5778#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21f6 5779#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 5780 5781 5782// addressBlock: dce_dc_dio_dp1_dispdec 5783// base address: 0x400 5784#define mmDP1_DP_LINK_CNTL 0x2208 5785#define mmDP1_DP_LINK_CNTL_BASE_IDX 2 5786#define mmDP1_DP_PIXEL_FORMAT 0x2209 5787#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 5788#define mmDP1_DP_MSA_COLORIMETRY 0x220a 5789#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 5790#define mmDP1_DP_CONFIG 0x220b 5791#define mmDP1_DP_CONFIG_BASE_IDX 2 5792#define mmDP1_DP_VID_STREAM_CNTL 0x220c 5793#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 5794#define mmDP1_DP_STEER_FIFO 0x220d 5795#define mmDP1_DP_STEER_FIFO_BASE_IDX 2 5796#define mmDP1_DP_MSA_MISC 0x220e 5797#define mmDP1_DP_MSA_MISC_BASE_IDX 2 5798#define mmDP1_DP_VID_TIMING 0x2210 5799#define mmDP1_DP_VID_TIMING_BASE_IDX 2 5800#define mmDP1_DP_VID_N 0x2211 5801#define mmDP1_DP_VID_N_BASE_IDX 2 5802#define mmDP1_DP_VID_M 0x2212 5803#define mmDP1_DP_VID_M_BASE_IDX 2 5804#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213 5805#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 5806#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214 5807#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 5808#define mmDP1_DP_VID_MSA_VBID 0x2215 5809#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 5810#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216 5811#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 5812#define mmDP1_DP_DPHY_CNTL 0x2217 5813#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2 5814#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 5815#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 5816#define mmDP1_DP_DPHY_SYM0 0x2219 5817#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2 5818#define mmDP1_DP_DPHY_SYM1 0x221a 5819#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2 5820#define mmDP1_DP_DPHY_SYM2 0x221b 5821#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2 5822#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c 5823#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 5824#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d 5825#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 5826#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e 5827#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 5828#define mmDP1_DP_DPHY_CRC_EN 0x221f 5829#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 5830#define mmDP1_DP_DPHY_CRC_CNTL 0x2220 5831#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 5832#define mmDP1_DP_DPHY_CRC_RESULT 0x2221 5833#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 5834#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222 5835#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 5836#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223 5837#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 5838#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224 5839#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 5840#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 5841#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 5842#define mmDP1_DP_SEC_CNTL 0x222b 5843#define mmDP1_DP_SEC_CNTL_BASE_IDX 2 5844#define mmDP1_DP_SEC_CNTL1 0x222c 5845#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2 5846#define mmDP1_DP_SEC_FRAMING1 0x222d 5847#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 5848#define mmDP1_DP_SEC_FRAMING2 0x222e 5849#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 5850#define mmDP1_DP_SEC_FRAMING3 0x222f 5851#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 5852#define mmDP1_DP_SEC_FRAMING4 0x2230 5853#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 5854#define mmDP1_DP_SEC_AUD_N 0x2231 5855#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2 5856#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232 5857#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 5858#define mmDP1_DP_SEC_AUD_M 0x2233 5859#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2 5860#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234 5861#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 5862#define mmDP1_DP_SEC_TIMESTAMP 0x2235 5863#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 5864#define mmDP1_DP_SEC_PACKET_CNTL 0x2236 5865#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 5866#define mmDP1_DP_MSE_RATE_CNTL 0x2237 5867#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 5868#define mmDP1_DP_MSE_RATE_UPDATE 0x2239 5869#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 5870#define mmDP1_DP_MSE_SAT0 0x223a 5871#define mmDP1_DP_MSE_SAT0_BASE_IDX 2 5872#define mmDP1_DP_MSE_SAT1 0x223b 5873#define mmDP1_DP_MSE_SAT1_BASE_IDX 2 5874#define mmDP1_DP_MSE_SAT2 0x223c 5875#define mmDP1_DP_MSE_SAT2_BASE_IDX 2 5876#define mmDP1_DP_MSE_SAT_UPDATE 0x223d 5877#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 5878#define mmDP1_DP_MSE_LINK_TIMING 0x223e 5879#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 5880#define mmDP1_DP_MSE_MISC_CNTL 0x223f 5881#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 5882#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 5883#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 5884#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 5885#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 5886#define mmDP1_DP_MSE_SAT0_STATUS 0x2247 5887#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 5888#define mmDP1_DP_MSE_SAT1_STATUS 0x2248 5889#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 5890#define mmDP1_DP_MSE_SAT2_STATUS 0x2249 5891#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 5892#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c 5893#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 5894#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d 5895#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 5896#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e 5897#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 5898#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f 5899#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 5900#define mmDP1_DP_DSC_CNTL 0x2252 5901#define mmDP1_DP_DSC_CNTL_BASE_IDX 2 5902#define mmDP1_DP_SEC_CNTL2 0x2253 5903#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2 5904#define mmDP1_DP_SEC_CNTL3 0x2254 5905#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2 5906#define mmDP1_DP_SEC_CNTL4 0x2255 5907#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2 5908#define mmDP1_DP_SEC_CNTL5 0x2256 5909#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2 5910#define mmDP1_DP_SEC_CNTL6 0x2257 5911#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2 5912#define mmDP1_DP_SEC_CNTL7 0x2258 5913#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2 5914#define mmDP1_DP_DB_CNTL 0x2259 5915#define mmDP1_DP_DB_CNTL_BASE_IDX 2 5916#define mmDP1_DP_MSA_VBID_MISC 0x225a 5917#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2 5918#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b 5919#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 5920#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c 5921#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 5922 5923 5924// addressBlock: dce_dc_dcio_dcio_dispdec 5925// base address: 0x0 5926#define mmDC_GENERICA 0x2868 5927#define mmDC_GENERICA_BASE_IDX 2 5928#define mmUNIPHYA_LINK_CNTL 0x286d 5929#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2 5930#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 5931#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 5932#define mmUNIPHYB_LINK_CNTL 0x286f 5933#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2 5934#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 5935#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 5936#define mmDCIO_WRCMD_DELAY 0x287e 5937#define mmDCIO_WRCMD_DELAY_BASE_IDX 2 5938#define mmDC_PINSTRAPS 0x2880 5939#define mmDC_PINSTRAPS_BASE_IDX 2 5940#define mmDCIO_CLOCK_CNTL 0x2895 5941#define mmDCIO_CLOCK_CNTL_BASE_IDX 2 5942#define mmDCIO_SOFT_RESET 0x289e 5943#define mmDCIO_SOFT_RESET_BASE_IDX 2 5944 5945 5946// addressBlock: dce_dc_dcio_dcio_chip_dispdec 5947// base address: 0x0 5948#define mmDC_GPIO_DDC1_MASK 0x28d0 5949#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2 5950#define mmDC_GPIO_DDC1_A 0x28d1 5951#define mmDC_GPIO_DDC1_A_BASE_IDX 2 5952#define mmDC_GPIO_DDC1_EN 0x28d2 5953#define mmDC_GPIO_DDC1_EN_BASE_IDX 2 5954#define mmDC_GPIO_DDC1_Y 0x28d3 5955#define mmDC_GPIO_DDC1_Y_BASE_IDX 2 5956#define mmDC_GPIO_DDC2_MASK 0x28d4 5957#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2 5958#define mmDC_GPIO_DDC2_A 0x28d5 5959#define mmDC_GPIO_DDC2_A_BASE_IDX 2 5960#define mmDC_GPIO_DDC2_EN 0x28d6 5961#define mmDC_GPIO_DDC2_EN_BASE_IDX 2 5962#define mmDC_GPIO_DDC2_Y 0x28d7 5963#define mmDC_GPIO_DDC2_Y_BASE_IDX 2 5964#define mmDC_GPIO_HPD_MASK 0x28f4 5965#define mmDC_GPIO_HPD_MASK_BASE_IDX 2 5966#define mmDC_GPIO_HPD_A 0x28f5 5967#define mmDC_GPIO_HPD_A_BASE_IDX 2 5968#define mmDC_GPIO_HPD_EN 0x28f6 5969#define mmDC_GPIO_HPD_EN_BASE_IDX 2 5970#define mmDC_GPIO_HPD_Y 0x28f7 5971#define mmDC_GPIO_HPD_Y_BASE_IDX 2 5972#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc 5973#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 5974#define mmPHY_AUX_CNTL 0x28ff 5975#define mmPHY_AUX_CNTL_BASE_IDX 2 5976#define mmDC_GPIO_AUX_CTRL_1 0x2917 5977#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 5978#define mmDC_GPIO_AUX_CTRL_2 0x2918 5979#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 5980#define mmDC_GPIO_AUX_CTRL_3 0x291b 5981#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2 5982#define mmDC_GPIO_AUX_CTRL_4 0x291c 5983#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2 5984#define mmDC_GPIO_AUX_CTRL_5 0x291d 5985#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2 5986#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e 5987#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 5988 5989// addressBlock: azf0endpoint0_endpointind 5990// base address: 0x0 5991#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 5992#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 5993#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 5994#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 5995#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 5996#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 5997#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 5998#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 5999#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 6000#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 6001#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 6002#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 6003#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 6004#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 6005#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 6006#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 6007#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 6008#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 6009#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 6010#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 6011#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 6012#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 6013#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 6014#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 6015#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 6016#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 6017#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 6018#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 6019#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 6020#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 6021#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 6022#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 6023#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 6024#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 6025#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 6026#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 6027#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 6028#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 6029#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 6030#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 6031#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 6032#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 6033#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 6034#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 6035#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 6036#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 6037#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 6038#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 6039#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 6040#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 6041#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 6042#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 6043#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 6044#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 6045#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 6046#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 6047#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 6048#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 6049#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 6050#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 6051#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 6052#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 6053#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 6054#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 6055#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 6056#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 6057#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 6058#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 6059#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 6060#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 6061#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 6062 6063 6064// addressBlock: azf0endpoint1_endpointind 6065// base address: 0x0 6066#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 6067#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 6068#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 6069#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 6070#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 6071#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 6072#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 6073#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 6074#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 6075#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 6076#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 6077#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 6078#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 6079#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 6080#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 6081#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 6082#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 6083#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 6084#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 6085#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 6086#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 6087#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 6088#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 6089#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 6090#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 6091#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 6092#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 6093#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 6094#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 6095#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 6096#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 6097#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 6098#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 6099#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 6100#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 6101#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 6102#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 6103#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 6104#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 6105#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 6106#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 6107#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 6108#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 6109#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 6110#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 6111#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 6112#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 6113#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 6114#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 6115#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 6116#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 6117#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 6118#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 6119#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 6120#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 6121#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 6122#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 6123#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 6124#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 6125#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 6126#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 6127#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 6128#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 6129#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 6130#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 6131#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 6132#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 6133#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 6134#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 6135#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 6136#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 6137 6138 6139// addressBlock: azf0inputendpoint0_inputendpointind 6140// base address: 0x0 6141#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 6142#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 6143#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 6144#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 6145#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 6146#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 6147#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 6148#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 6149#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 6150#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 6151#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 6152#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 6153#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 6154#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 6155#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 6156#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 6157#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 6158#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 6159#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 6160#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 6161#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 6162#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 6163#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 6164 6165 6166// addressBlock: azf0inputendpoint1_inputendpointind 6167// base address: 0x0 6168#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 6169#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 6170#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 6171#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 6172#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 6173#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 6174#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 6175#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 6176#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 6177#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 6178#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 6179#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 6180#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 6181#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 6182#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 6183#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 6184#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 6185#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 6186#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 6187#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 6188#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 6189#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 6190#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 6191 6192 6193#endif 6194