Searched refs:mdiv (Results 1 - 4 of 4) sorted by relevance
| /openbsd-current/sys/arch/armv7/exynos/ |
| H A D | exclock.c | 237 uint32_t kdiv, mdiv, pdiv, sdiv; local
278 mdiv = (reg >> 16) & 0x1ff;
285 freq = ((mdiv << 16) + kdiv) * freq / (pdiv * (1 << sdiv));
289 mdiv = (reg >> 16) & 0x3ff;
294 return mdiv * freq / (pdiv * (1 << sdiv));
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| /openbsd-current/sys/arch/macppc/dev/ |
| H A D | i2s.c | 670 * MCLK = clksrc / mdiv
679 int clksrc, mdiv, sdiv; local
707 mdiv = clksrc / MCLK; /* 4 */
710 switch (mdiv) {
721 reg |= ((mdiv / 2 - 1) << 24) & 0x1f000000;
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| /openbsd-current/sys/dev/pci/drm/i915/display/ |
| H A D | intel_dpll.c | 1664 u32 mdiv; local
1694 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
1695 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
1696 mdiv |= ((bestn << DPIO_N_SHIFT));
1697 mdiv |= (1 << DPIO_K_SHIFT);
1704 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
1705 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
1707 mdiv |= DPIO_ENABLE_CALIBRATION;
1708 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
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| H A D | intel_display.c | 2797 u32 mdiv; local
2805 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
2808 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
2809 clock.m2 = mdiv & DPIO_M2DIV_MASK;
2810 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
2811 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
2812 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
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