Searched refs:ixGCK_DFS_BYPASS_CNTL (Results 1 - 9 of 9) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ |
| H A D | polaris_baco.c | 62 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL },
148 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL },
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| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | vce_v4_0.c | 909 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
916 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
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| H A D | uvd_v7_0.c | 1710 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1719 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/smu/ |
| H A D | smu_7_0_0_d.h | 44 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 macro
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| H A D | smu_7_1_0_d.h | 44 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 macro
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| H A D | smu_7_1_1_d.h | 44 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 macro
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| H A D | smu_7_0_1_d.h | 44 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 macro
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| H A D | smu_7_1_3_d.h | 47 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 macro
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| H A D | smu_7_1_2_d.h | 44 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 macro
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